
ADC07D1520CIYB/NOPB
Active7-BIT, DUAL 1.5-GSPS OR SINGLE 3.0-GSPS ANALOG-TO-DIGITAL CONVERTER (ADC)
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ADC07D1520CIYB/NOPB
Active7-BIT, DUAL 1.5-GSPS OR SINGLE 3.0-GSPS ANALOG-TO-DIGITAL CONVERTER (ADC)
Technical Specifications
Parameters and characteristics for this part
| Specification | ADC07D1520CIYB/NOPB |
|---|---|
| Architecture | Folding Interpolating |
| Configuration | MUX-S/H-ADC |
| Data Interface | LVDS - Parallel |
| Features | Simultaneous Sampling |
| Input Type | Differential |
| Mounting Type | Surface Mount |
| Number of A/D Converters | 2 |
| Number of Inputs | 2 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Ratio - S/H:ADC | 1:1 |
| Reference Type | Internal |
| Sampling Rate (Per Second) | 3 G |
| Supplier Device Package | 128-HLQFP (20x20) |
| Voltage - Supply, Analog [Max] | 2 V |
| Voltage - Supply, Analog [Min] | 1.8 V |
| Voltage - Supply, Digital [Max] | 2 V |
| Voltage - Supply, Digital [Min] | 1.8 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 1 | $ 187.42 | |
| 10 | $ 179.50 | |||
| Texas Instruments | JEDEC TRAY (10+1) | 1 | $ 151.59 | |
| 100 | $ 137.21 | |||
| 250 | $ 133.29 | |||
| 1000 | $ 130.68 | |||
Description
General part information
ADC07D1520 Series
The ADC07D1520 is a dual, low power, high performance CMOS analog-to-digital converter. The ADC07D1520 digitizes signals to 7 bits of resolution at sample rates up to 1.5 GSPS. Its features include a test pattern output for system debug, a clock phase adjust, and selectable output demultiplexer modes. This device is guaranteed to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 6.8 Effective Number of Bits (ENOB) with a 748 MHz input signal and a 1.5 GHz sample rate while providing a 10-18Code Error Rate (C.E.R.) Output formatting is offset binary and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V.
Each converter has a selectable output demultiplexer which feeds two LVDS buses. If the 1:2 Demultiplexed Mode is selected, the output data rate is reduced to half the input sample rate on each bus. When Non-Demultiplexed Mode is selected, the output data rate on channels DI and DQ is at the same rate as the input sample clock. The two converters can be interleaved and used as a single 3 GSPS ADC.
The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a leaded or lead-free, 128-pin, thermally enhanced, exposed pad LQFP and operates over the Industrial (–40°C ≤ TA≤ +85°C) temperature range.
Documents
Technical documentation and resources