
ADS6142IRHBT
Active1-CHANNEL SINGLE ADC PIPELINED 65MSPS 14-BIT PARALLEL/SERIAL/LVDS 32-PIN VQFN EP T/R
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ADS6142IRHBT
Active1-CHANNEL SINGLE ADC PIPELINED 65MSPS 14-BIT PARALLEL/SERIAL/LVDS 32-PIN VQFN EP T/R
Technical Specifications
Parameters and characteristics for this part
| Specification | ADS6142IRHBT |
|---|---|
| Architecture | Pipelined |
| Configuration | S/H-ADC |
| Data Interface | LVDS - Parallel, Parallel |
| Input Type | Differential |
| Mounting Type | Surface Mount |
| Number of A/D Converters | 1 |
| Number of Bits | 14 |
| Number of Inputs | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 32-VFQFN Exposed Pad |
| Ratio - S/H:ADC | 1:1 |
| Reference Type | External, Internal |
| Sampling Rate (Per Second) | 65 M |
| Supplier Device Package | 32-VQFN (5x5) |
| Voltage - Supply, Analog [Max] | 3.6 V |
| Voltage - Supply, Analog [Min] | 3 V |
| Voltage - Supply, Digital [Max] | 3.6 V |
| Voltage - Supply, Digital [Min] | 1.65 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 39.38 | |
| 10 | $ 36.74 | |||
| 25 | $ 35.20 | |||
| 100 | $ 31.90 | |||
| Digi-Reel® | 1 | $ 39.38 | ||
| 10 | $ 36.74 | |||
| 25 | $ 35.20 | |||
| 100 | $ 31.90 | |||
| Tape & Reel (TR) | 250 | $ 30.80 | ||
| Texas Instruments | SMALL T&R | 1 | $ 33.33 | |
| 100 | $ 29.63 | |||
| 250 | $ 24.36 | |||
| 1000 | $ 21.78 | |||
Description
General part information
ADS6142 Series
ADS6145/ADS6144/ADS6143/ADS6142 (ADS614X) are a family of 14-bit A/D converters with sampling frequencies up to 125 MSPS. The high performance and low power consumption of the ADS614X are combined in a compact 32 QFN package. An internal high bandwidth sample and hold and a low jitter clock buffer help to achieve high SNR and high SFDR even at high input frequencies.
The ADS614X feature coarse and fine gain options to improve SFDR performance at lower full-scale analog input ranges.
The digital data outputs are either parallel CMOS or DDR (Double Data Rate) LVDS. Several features exist to ease data capture such as — controls for output clock position and output buffer drive strength, LVDS current, and internal termination programmability.
Documents
Technical documentation and resources