Integrated Circuits (ICs)

SN74LVC2G101BQBR

Active

TWO-CHANNEL 1.1V-TO-3.6V CONFIGURABLE GATE FOR CLOCK INPUT WITH SCHMITT-TRIGGER INPUTS

Deep-Dive with AI

Search across all available documentation for this part.

DocumentsPower-Up 3-State (PU3S) Circuits in TI Standard Logic Devices SN74LVC2G101 Dual D-Type Flip-Flop with Configurable Multiple-Function Gated Clock datasheet +25

Integrated Circuits (ICs)

SN74LVC2G101BQBR

Active

Texas Instruments

TWO-CHANNEL 1.1V-TO-3.6V CONFIGURABLE GATE FOR CLOCK INPUT WITH SCHMITT-TRIGGER INPUTS

Deep-Dive with AI

DocumentsPower-Up 3-State (PU3S) Circuits in TI Standard Logic Devices SN74LVC2G101 Dual D-Type Flip-Flop with Configurable Multiple-Function Gated Clock datasheet +25

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	SN74LVC2G101BQBR

null

SN74LVC2G101 Series

Two-channel 1.1V-to-3.6V configurable gate for clock input with Schmitt-trigger inputs

Part
Texas Instruments SN74LVC2G101BQBR

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tape & Reel (TR)	3000	$ 0.39
		6000	$ 0.37
		15000	$ 0.36
Texas Instruments	LARGE T&R	1	$ 0.69
		100	$ 0.53
		250	$ 0.39
		1000	$ 0.28

Description

General part information

SN74LVC2G101 Series

The SN74LVC2G101 contains two independent D-type flip-flops. Each channel has data (D), clear (CLR), and clock (CLKA, CLKB, CLKC, CLKD) inputs and a non-inverted output (Q). The clock inputs can be configured for use in a wide variety of applications, allowing for configuration as 2-input AND, OR, NAND, NOR, XOR, XNOR, as well as 1-input inverted or non-inverted operation. All inputs include Schmitt-trigger architecture.

Documents

Technical documentation and resources

SN74LVC2G101BQBR

Deep-Dive with AI

SN74LVC2G101BQBR

Deep-Dive with AI

Technical Specifications

SN74LVC2G101 Series

Pricing

Description

SN74LVC2G101 Series

Documents

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

SN74LVC2G101 Dual D-Type Flip-Flop with Configurable Multiple-Function Gated Clock datasheet

LOGIC Pocket Data Book (Rev. B)

Understanding Advanced Bus-Interface Products Design Guide

Implications of Slow or Floating CMOS Inputs (Rev. E)

Live Insertion

CMOS Power Consumption and CPD Calculation (Rev. B)

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Selecting the Right Level Translation Solution (Rev. A)

Signal Switch Data Book (Rev. A)

STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Use of the CMOS Unbuffered Inverter in Oscillator Circuits

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Logic Guide (Rev. AB)

Low-Voltage Logic (LVC) Designer's Guide

Design Summary for WCSP Little Logic (Rev. B)

Input and Output Characteristics of Digital Integrated Circuits

LVC Characterization Information

Texas Instruments Little Logic Application Report

TI IBIS File Creation, Validation, and Distribution Processes

Standard Linear & Logic for PCs, Servers & Motherboards

Little Logic Guide 2018 (Rev. G)

Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices

How to Select Little Logic (Rev. A)

LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)

SN74LVC2G101 Series