Specification	SN74ACT573DWR

Circuit [custom]	8
Circuit [custom]	8
Current - Output High, Low	24 mA
Delay Time - Propagation	6 ns
Independent Circuits	1
Logic Type	D-Type Transparent Latch
Mounting Type	Surface Mount
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output Type	Tri-State
Package / Case	20-SOIC
Package / Case [y]	0.295 in
Package / Case [y]	7.5 mm
Supplier Device Package	20-SOIC
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	4.5 V

CD74ACT573 Series

Octal Non-Inverting Transparent Latches with 3-State Outputs

Part	Operating Temperature [Max]	Operating Temperature [Min]	Independent Circuits	Voltage - Supply [Min]	Voltage - Supply [Max]	Current - Output High, Low	Delay Time - Propagation	Output Type	Supplier Device Package	Circuit [custom]	Circuit [custom]	Mounting Type	Logic Type	Package / Case [y]	Package / Case	Package / Case [x]	Package / Case	Package / Case	Package / Case [y]
Texas Instruments SN74ACT573PWR	85 °C	-40 °C	1	4.5 V	5.5 V	24 mA	6 ns	Tri-State	20-TSSOP	8	8	Surface Mount	D-Type Transparent Latch	4.4 mm	20-TSSOP	0.173 in
Texas Instruments SN74ACT573NSR	85 °C	-40 °C	1	4.5 V	5.5 V	24 mA	6 ns	Tri-State	20-SO	8	8	Surface Mount	D-Type Transparent Latch		20-SOIC		0.209 "	5.3 mm
Texas Instruments CD74ACT573E	125 °C	-55 °C	1	4.5 V	5.5 V	24 mA	3.1 ns	Tri-State	20-PDIP	8	8	Through Hole	D-Type Transparent Latch		20-DIP		0.3 in	7.62 mm
Texas Instruments SN74ACT573DWR	85 °C	-40 °C	1	4.5 V	5.5 V	24 mA	6 ns	Tri-State	20-SOIC	8	8	Surface Mount	D-Type Transparent Latch	0.295 in	20-SOIC				7.5 mm
Texas Instruments SN74ACT573N	85 °C	-40 °C	1	4.5 V	5.5 V	24 mA	6 ns	Tri-State	20-PDIP	8	8	Through Hole	D-Type Transparent Latch		20-DIP		0.3 in	7.62 mm
Texas Instruments CD74ACT573M96	125 °C	-55 °C	1	4.5 V	5.5 V	24 mA	3.1 ns	Tri-State	20-SOIC	8	8	Surface Mount	D-Type Transparent Latch	0.295 in	20-SOIC				7.5 mm
Texas Instruments SN74ACT573DBR	85 °C	-40 °C	1	4.5 V	5.5 V	24 mA	6 ns	Tri-State	20-SSOP	8	8	Surface Mount	D-Type Transparent Latch		20-SSOP
Texas Instruments SN74ACT573DWRG4	85 °C	-40 °C	1	4.5 V	5.5 V	24 mA	6 ns	Tri-State	20-SOIC	8	8	Surface Mount	D-Type Transparent Latch	0.295 in	20-SOIC				7.5 mm
Texas Instruments SN74ACT573RKSR	125 °C	-40 °C	1	4.5 V	5.5 V	24 mA	6 ns	Non-Inverted Tri-State	20-VQFN (2.5x4.5)	8	8	Surface Mount	D-Type Transparent Latch		20-VFQFN Exposed Pad
Texas Instruments SN74ACT573PWRE4	85 °C	-40 °C	1	4.5 V	5.5 V	24 mA	6 ns	Tri-State	20-TSSOP	8	8	Surface Mount	D-Type Transparent Latch	4.4 mm	20-TSSOP	0.173 in

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 0.79
		10	$ 0.69
		25	$ 0.65
		100	$ 0.53
		250	$ 0.50
		500	$ 0.42
		1000	$ 0.34
	Digi-Reel®	1	$ 0.79
		10	$ 0.69
		25	$ 0.65
		100	$ 0.53
		250	$ 0.50
		500	$ 0.42
		1000	$ 0.34
	Tape & Reel (TR)	2000	$ 0.31
		6000	$ 0.28
		10000	$ 0.27
Texas Instruments	LARGE T&R	1	$ 0.57
		100	$ 0.43
		250	$ 0.32
		1000	$ 0.23

Description

General part information

CD74ACT573 Series

The RCA-CD54/74AC563 and CD54/74AC573 and the CD54/74ACT563 and CD54/74ACT573 octal transparent 3-state latches use the RCA ADVANCED CMOS technology. The outputs are transparent to the inputs when the Latch Enable (LE\) is HIGH. When the Latch Enable (LE\) goes LOW, the data is latched. The Output Enable (OE\) controls the 3-state ouputs. When the Output Enable (OE\) is HIGH, the outputs are in the high-impendance state. The latch operation is independent of the state of the Output Enable.

The CD74AC/ACT563 and CD74AC/ACT573 are supplied in 20-lead dual-in-line plastic packages (E suffix) and in 20-lead dual-in-line small-outline plastic packages (M suffix). Both package types are operable over the folowing temperature ranges: Commerical (0 to 70°C); Industrial (-40 to +85°C); and Extended Industrial/Military (-55 to +125°C).

The CD54AC/ACT563 and CD54AC/ACT573, available in chip form (H suffix), are operable over the -55 to +125°C temperature range.

Documents

Technical documentation and resources

Datasheet

SN74ACT573DWR

Deep-Dive with AI

SN74ACT573DWR

Deep-Dive with AI

Technical Specifications

CD74ACT573 Series

Pricing

Description

CD74ACT573 Series

Documents

Datasheet

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Designing With Logic (Rev. C)

CMOS Power Consumption and CPD Calculation (Rev. B)

TI IBIS File Creation, Validation, and Distribution Processes

Power-Up Behavior of Clocked Devices (Rev. B)

Implications of Slow or Floating CMOS Inputs (Rev. E)

Selecting the Right Level Translation Solution (Rev. A)

Logic Guide (Rev. AB)

Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

LOGIC Pocket Data Book (Rev. B)

CD74ACT573 Series