Integrated Circuits (ICs)

DRA746PPIGABZQ1

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MULTI-CORE SOC PROCESSORS WITH ISP AND PIN-COMPATIBLE WITH DRA74X SOC PROCESSORS

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Search across all available documentation for this part.

DocumentsTools and Techniques for Audio Debugging DRA77xP, DRA76xP, DRA75xP, DRA74xP Technical Reference Manual (Rev. D)+38

Integrated Circuits (ICs)

DRA746PPIGABZQ1

Active

Texas Instruments

MULTI-CORE SOC PROCESSORS WITH ISP AND PIN-COMPATIBLE WITH DRA74X SOC PROCESSORS

Deep-Dive with AI

DocumentsTools and Techniques for Audio Debugging DRA77xP, DRA76xP, DRA75xP, DRA74xP Technical Reference Manual (Rev. D)+38

Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	DRA746PPIGABZQ1

Additional Interfaces	McASP, SPI, UART, MMC/SD, I2C
Co-Processors/DSP	C66x, ARM® Cortex®-M4, IVA
Core Processor	ARM® Cortex®-A15
Display & Interface Controllers	HDMI, LCD
Ethernet	10/100Mbps (1), 10/100/1000Mbps (1)
Grade	Automotive
Graphics Acceleration	True
Mounting Type	Surface Mount
Number of Cores/Bus Width [custom]	32 Bit
Number of Cores/Bus Width [custom]	2
Operating Temperature [Max]	125 ¯C
Operating Temperature [Min]	-40 °C
Package / Case	760-LFBGA, FCBGA
Qualification	AEC-Q100
RAM Controllers	DDR2, DDR3L, DDR3
SATA	SATA
Security Features	Boot Security, Secure Debug
Speed	1.5 GHz
Supplier Device Package	760-FCBGA (23x23)
USB	USB 2.0 (3), USB 3.0 (1)
Voltage - I/O	1.5 V, 1.35 V, 3.3 V, 1.8 V

DRA74P Series

Multi-core SoC processors with ISP and pin-compatible with DRA74x SoC processors

Part	Voltage - I/O	Supplier Device Package	Display & Interface Controllers	USB	Package / Case	Core Processor	Number of Cores/Bus Width [custom]	Number of Cores/Bus Width [custom]	Co-Processors/DSP	Security Features	Grade	Mounting Type	SATA	Graphics Acceleration	Speed	Ethernet	Additional Interfaces	RAM Controllers	Operating Temperature [Min]	Operating Temperature [Max]	Qualification
Texas Instruments DRA746PPIGABZQ1	1.35 V 1.5 V 1.8 V 3.3 V	760-FCBGA (23x23)	HDMI LCD	USB 2.0 (3) USB 3.0 (1)	760-LFBGA FCBGA	ARM® Cortex®-A15	32 Bit	2	ARM® Cortex®-M4 C66x IVA	Boot Security Secure Debug	Automotive	Surface Mount	SATA		1.5 GHz	10/100/1000Mbps (1) 10/100Mbps (1)	I2C McASP MMC/SD SPI UART	DDR2 DDR3 DDR3L	-40 °C	125 ¯C	AEC-Q100

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Description

General part information

DRA74P Series

DRA74xP and DRA75xP (Jacinto 6 Plus) automotive applications processors are built to meet the intense processing needs of the modern digital cockpit automobile experiences.

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 Plus devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.

Programmability is provided by dual-core Arm Cortex-A15 RISC CPUs with Neon™ extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Documents

Technical documentation and resources

DRA746PPIGABZQ1

Deep-Dive with AI

DRA746PPIGABZQ1

Deep-Dive with AI

Technical Specifications

DRA74P Series

Pricing

Description

DRA74P Series

Documents

Tools and Techniques for Audio Debugging

DRA77xP, DRA76xP, DRA75xP, DRA74xP Technical Reference Manual (Rev. D)

Modifying Memory Usage for IPUMM Applications Loaded IPC 3.x for DRA75x, DRA74x (Rev. A)

Informational ADAS as Software Upgrade to Today’s Infotainment Systems

Integrating AUTOSAR on TI SoC: Fundamentals

DRA75xP, DRA74xP Infotainment Applications Processor Silicon Revision 1.0 datasheet (Rev. F)

Sharing VPE Between VISIONSDK and PSDKLA

The Implementation of YUV422 Output for SRV

Debugging Tools and Techniques With IPC3.x

AM57x, DRA7x, and TDA2x EMIF Tools (Rev. E)

Tools and Techniques to Root Case Failures in Video Capture Subsystem

ECC/EDC on TDAxx (Rev. B)

Revolutionize the automotive cockpit

Jacinto6 Android Video Decoder Software Design Specification User's Guide

Optimization of GPU-Based Surround View on TI’s TDA2x SoC

Flashing Binaries to DRA7xx Factory Boards Using DFU

Building your application with security in mind (Rev. E)

Quality of Service (QoS) Knobs for DRA74x, DRA75x & TDA2x Family of Devices (Rev. A)

Optimizing DRA7xx and TDA2xx Processors for use with Video Display SERDES (Rev. B)

Jacinto6 Android Video Encoder Software Design Specification User's Guide

Software Guidelines to EMIF/DDR3 Configuration on DRA7xx Devices

Flashing Utility - mflash

Integrating virtual DRM between VISION SDK and PSDK on Jacinto6 SOC

Using DSS Write-Back Pipeline for RGB-to-YUV Conversion on DRA7xx Devices

IVA-HD Sharing Between VISION-SDK and PSDKLA on Jacinto6 SoC

Using Peripheral Boot and DFU for Rapid Development on Jacinto 6 Devices (Rev. A)

Early Splash Screen on DRA7x Devices

Gstreamer Migration Guidelines

DRA7xx Silicon Errata (Rev. B)

Android Boot Optimization on DRA7xx Devices (Rev. A)

Integrating New Cameras With Video Input Port on DRA7xx SoCs

Achieving Early CAN Response on DRA7xx Devices

Guide to fix Perf Issues Using QoS Knobs for DRA74x, DRA75x, TDA2x & TD3x Device

Today’s high-end infotainment soon becoming mainstream

MMC DLL Tuning (Rev. B)

Interfacing DRA75x and DRA74x Audio to Analog Codecs (Rev. A)

Audio Post Processing Engine on Jacinto™ DRA7x Family of Devices

Linux Boot Time Optimizations on DRA7xx Devices

A Guide to Debugging With CCS on the DRA75x, DRA74x, TDA2x and TDA3x Family of D (Rev. B)

DRA74x_75x/DRA72x Performance (Rev. A)

DRA74P Series