SN74HCS574QWRKSRQ1
ActiveAUTOMOTIVE OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH THREE-STATE OUTPUTS
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SN74HCS574QWRKSRQ1
ActiveAUTOMOTIVE OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH THREE-STATE OUTPUTS
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74HCS574QWRKSRQ1 |
|---|---|
| Clock Frequency | 135 MHz |
| Current - Output High, Low [custom] | 7.8 mA |
| Current - Output High, Low [custom] | 7.8 mA |
| Current - Quiescent (Iq) | 2 µA |
| Function | Standard |
| Input Capacitance | 5 pF |
| Max Propagation Delay @ V, Max CL | 11 ns |
| Mounting Type | Wettable Flank, Surface Mount |
| Number of Bits per Element | 8 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Tri-State |
| Package / Case | 20-VFQFN Exposed Pad |
| Supplier Device Package | 20-VQFN (2.5x4.5) |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 6 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 0.81 | |
| 10 | $ 0.71 | |||
| 25 | $ 0.67 | |||
| 100 | $ 0.55 | |||
| 250 | $ 0.51 | |||
| 500 | $ 0.43 | |||
| 1000 | $ 0.35 | |||
| Digi-Reel® | 1 | $ 0.81 | ||
| 10 | $ 0.71 | |||
| 25 | $ 0.67 | |||
| 100 | $ 0.55 | |||
| 250 | $ 0.51 | |||
| 500 | $ 0.43 | |||
| 1000 | $ 0.35 | |||
| Tape & Reel (TR) | 3000 | $ 0.27 | ||
| Texas Instruments | LARGE T&R | 1 | $ 0.50 | |
| 100 | $ 0.34 | |||
| 250 | $ 0.26 | |||
| 1000 | $ 0.17 | |||
Description
General part information
SN74HCS574-Q1 Series
The SN74HCS574-Q1 contains eight D-type flip-flops. All inputs include Schmitt-trigger architecture. All channels share a rising edge triggered clock (CLK) input and active low output enable (OE) input. This device has a flow-through pinout which allows for easier bus routing.
The SN74HCS574-Q1 contains eight D-type flip-flops. All inputs include Schmitt-trigger architecture. All channels share a rising edge triggered clock (CLK) input and active low output enable (OE) input. This device has a flow-through pinout which allows for easier bus routing.
Documents
Technical documentation and resources