LMK05318BRGZR
ActiveULTRA-LOW JITTER SINGLE CHANNEL NETWORK SYNCHRONIZER CLOCK WITH BAW
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LMK05318BRGZR
ActiveULTRA-LOW JITTER SINGLE CHANNEL NETWORK SYNCHRONIZER CLOCK WITH BAW
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | LMK05318BRGZR |
|---|---|
| Differential - Input:Output [custom] | True |
| Differential - Input:Output [custom] | True |
| Frequency - Max [Max] | 400 MHz, 1.25 GHz, 200 MHz |
| Input | LVCMOS |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output | LVCMOS, CML, LVPECL, HCSL, LVDS |
| Package / Case | 48-VFQFN Exposed Pad |
| PLL | Yes with Bypass |
| Ratio - Input:Output | 3:8 |
| Supplier Device Package | 48-VQFN (7x7) |
| Voltage - Supply [Max] | 3.465 V |
| Voltage - Supply [Min] | 3.135 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tape & Reel (TR) | 2500 | $ 10.28 | |
| Texas Instruments | LARGE T&R | 1 | $ 13.20 | |
| 100 | $ 11.53 | |||
| 250 | $ 8.89 | |||
| 1000 | $ 7.95 | |||
Description
General part information
LMK05318B Series
The LMK05318B is high-performance network synchronizer clock device that provides jitter cleaning, clock generation, advanced clock monitoring, and superior hitless switching performance to meet the stringent timing requirements of communications infrastructure and industrial applications. The ultra-low jitter and high power supply noise rejection (PSNR) of the device can reduce bit error rates (BER) in high-speed serial links.
The device can generate output clocks with 50-fs RMS jitter using TI’s proprietary Bulk Acoustic Wave (BAW) VCO technology, independent of the jitter and frequency of the XO and reference inputs.
The LMK05318B is high-performance network synchronizer clock device that provides jitter cleaning, clock generation, advanced clock monitoring, and superior hitless switching performance to meet the stringent timing requirements of communications infrastructure and industrial applications. The ultra-low jitter and high power supply noise rejection (PSNR) of the device can reduce bit error rates (BER) in high-speed serial links.
Documents
Technical documentation and resources