Specification	SN74ABT162841DLR

Circuit	10:10
Current - Output High, Low [custom]	12 mA
Current - Output High, Low [custom]	12 mA
Delay Time - Propagation	3.5 ns
Independent Circuits	2
Logic Type	D-Type Transparent Latch
Mounting Type	Surface Mount
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output Type	Tri-State
Package / Case	0.295 in
Package / Case	56-BSSOP
Package / Case	7.5 mm
Supplier Device Package	56-SSOP
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	4.5 V

SN74ABT162841 Series

20-Bit Bus-Interface D-Type Latches With 3-State Outputs

Part	Voltage - Supply [Min]	Voltage - Supply [Max]	Operating Temperature [Max]	Operating Temperature [Min]	Package / Case	Package / Case	Package / Case	Independent Circuits	Logic Type	Delay Time - Propagation	Supplier Device Package	Circuit	Output Type	Mounting Type	Current - Output High, Low [custom]	Current - Output High, Low [custom]
Texas Instruments SN74ABT162841DLR	4.5 V	5.5 V	85 °C	-40 °C	0.295 in	56-BSSOP	7.5 mm	2	D-Type Transparent Latch	3.5 ns	56-SSOP	10:10	Tri-State	Surface Mount	12 mA	12 mA
Texas Instruments SN74ABT162841DGGR	4.5 V	5.5 V	85 °C	-40 °C	0.24 in	56-TFSOP	6.1 mm	2	D-Type Transparent Latch	3.5 ns	56-TSSOP	10:10	Tri-State	Surface Mount	12 mA	12 mA

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 3.66
	Digi-Reel®	1	$ 3.66
	Tape & Reel (TR)	1000	$ 1.93
		2000	$ 1.84
		5000	$ 1.77
Texas Instruments	LARGE T&R	1	$ 2.76
		100	$ 2.42
		250	$ 1.70
		1000	$ 1.37

Description

General part information

SN74ABT162841 Series

These 20-bit transparent D-type latches feature noninverting 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The ’ABT162841 devices can be used as two 10-bit latches or one 20-bit latch. While the latch-enable (1LE or 2LE) input is high, the Q outputs of the corresponding 10-bit latch follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (1OE\ or 2OE\) input can be used to place the outputs of the corresponding 10-bit latch in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.

Documents

Technical documentation and resources

SN74ABT162841DLR

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SN74ABT162841DLR

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Technical Specifications

SN74ABT162841 Series

Pricing

Description

SN74ABT162841 Series

Documents

Live Insertion

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Selecting the Right Level Translation Solution (Rev. A)

Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B)

SN54ABT162841, SN74ABT162841 datasheet (Rev. C)

Advanced Bus Interface Logic Selection Guide

TI IBIS File Creation, Validation, and Distribution Processes

Understanding Advanced Bus-Interface Products Design Guide

Power-Up Behavior of Clocked Devices (Rev. B)

LOGIC Pocket Data Book (Rev. B)

Designing With Logic (Rev. C)

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

Logic Guide (Rev. AB)

Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A)

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Input and Output Characteristics of Digital Integrated Circuits

Quad Flatpack No-Lead Logic Packages (Rev. D)

Implications of Slow or Floating CMOS Inputs (Rev. E)

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A)

SN74ABT162841 Series