The TSB41BA3D provides the digital and analog transceiver functions needed to implement a three-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB41BA3D interfaces with a link-layer controller (LLC), such as the TSB82AA2, TSB12LV21, TSB12LV26, TSB12LV32, TSB42AA4, TSB42AB4, TSB12LV01B, or TSB12LV01C. It can also be connected via cable port to an integrated 1394 Link + PHY layer such as the TSB43AB2.

The TSB41BA3D is powered by a single 3.3-V supply. The core voltage supply is supplied by an internal voltage regulator to the PLLVDD-CORE and DVDD-CORE terminals. To protect the phase-locked loop (PLL) from noise, the PLLVDD-CORE terminals must be separately decoupled from the DVDD-CORE terminals. The PLLVDD-CORE terminals are decoupled with 1-µF and smaller decoupling capacitors and the DVDD-CORE terminals are separately decoupled with 1-µF and smaller decoupling capacitors. The separation between DVDD-CORE and PLLVDD-CORE must be implemented by separate power supply rails or planes.

The TSB41BA3D can be powered by dual supplies, a 3.3-V supply for I/O and a core voltage supply. The core voltage supply is supplied to the PLLVDD-CORE and DVDD-CORE terminals to the requirements in therecommended operating conditionssection of this data sheet. The PLLVDD-CORE terminals must be separated from the DVDD-CORE terminals, the PLLVDD-CORE terminals are decoupled with 1-µF and smaller decoupling capacitors and the DVDD-CORE terminals separately decoupled with 1-µF and smaller decoupling capacitors. The separation between DVDD-CORE and PLLVDD-CORE can be implemented by separate power supply rails, or by a single power supply rail, where the DVDD-CORE and PLLVDD-CORE are separated by a filter network to keep noise from the PLLVDD-CORE supply.Read more