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SQA48A
Integrated Circuits (ICs)

LMH0340SQE/NOPB

Active
Texas Instruments

3G HD/SD DVB-ASI SDI SERIALZIER AND DRIVER WITH LVDS INTERFACE

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Search across all available documentation for this part.

DocumentsAN-1943 Understanding Serial Digital Video Bit Rates (Rev. A)AN-1988 LMH0340 / LMH0341 SerDes Family LVDS Timing Overview (Rev. A)+12
SQA48A
Integrated Circuits (ICs)

LMH0340SQE/NOPB

Active
Texas Instruments

3G HD/SD DVB-ASI SDI SERIALZIER AND DRIVER WITH LVDS INTERFACE

Deep-Dive with AI

DocumentsAN-1943 Understanding Serial Digital Video Bit Rates (Rev. A)AN-1988 LMH0340 / LMH0341 SerDes Family LVDS Timing Overview (Rev. A)+12

Technical Specifications

Parameters and characteristics for this part

SpecificationLMH0340SQE/NOPB
ApplicationsVideo Equipment
InterfaceSMBus
Mounting TypeSurface Mount
Package / Case48-WFQFN Exposed Pad
Supplier Device Package48-WQFN (7x7)
Voltage - Supply2.5 V, 3.3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 35.72
10$ 32.94
25$ 31.46
100$ 28.13
Digi-Reel® 1$ 35.72
10$ 32.94
25$ 31.46
100$ 28.13
Tape & Reel (TR) 250$ 26.84
Texas InstrumentsSMALL T&R 1$ 28.04
100$ 24.92
250$ 20.49
1000$ 18.32

Description

General part information

LMH0340 Series

The LMH0340/0040/0070/0050 SDI Serializers are part of TI’s family of FPGA-Attach SER/DES products supporting 5-bit LVDS interfaces with FPGAs. An FPGA Host will format data with supplied IP such that the output of the LMH0340 is compliant with the requirements of DVB-ASI, SMPTE 259M-C, SMPTE 292M and SMPTE 424M standards. See for details on which Standards are supported per device.

The interface between the SER (Serializer) and the FPGA consists of a 5 bit wide LVDS data bus, an LVDS clock and an SMBus interface. The LMH0340/0040/0070 SER devices include an integrated cable driver which is fully compliant with all of the SMPTE specifications listed above. The LMH0050 has a CML output driver that can drive a differential transmission line or interface to a cable driver.

The FPGA-Attach SER/DES family is supported by a suite of IP which allows the design engineer to quickly develop video applications using the SER/DES products. The SER is packaged in a physically small 48-pin WQFN package.