
MT48LC2M32B2B5-6A IT:J
ActiveDRAM CHIP SDR SDRAM 64MBIT 2MX32 3.3V 90-PIN VFBGA TRAY
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MT48LC2M32B2B5-6A IT:J
ActiveDRAM CHIP SDR SDRAM 64MBIT 2MX32 3.3V 90-PIN VFBGA TRAY
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Technical Specifications
Parameters and characteristics for this part
| Specification | MT48LC2M32B2B5-6A IT:J |
|---|---|
| Access Time | 5.4 ns |
| Clock Frequency | 167 MHz |
| Memory Format | DRAM |
| Memory Interface | Parallel |
| Memory Organization | 2 M |
| Memory Size | 8 MB |
| Memory Type | Volatile |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 85 C |
| Operating Temperature [Min] | -40 ¯C |
| Package / Case | 90-VFBGA |
| Supplier Device Package | 90-VFBGA (8x13) |
| Technology | SDRAM |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 3 V |
| Write Cycle Time - Word, Page | 12 ns |
Pricing
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Description
General part information
MT48LC2M32B2 Series
MT48LC2M32B2B5-6A IT:J is a SDR SDRAM. It uses a 64Mb SDRAM and a high-speed CMOS, dynamic random-access memory containing 67,108,864 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 67,108,864-bit banks are organized as 8192 rows by 2048 columns by 4 bits. Each of the 16,777,216-bit banks are organized as 2048 rows by 256 columns by 32bits. It supports CAS latency (CL) of 1, 2, and 3.
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Technical documentation and resources