CDCLVD1204RGTR
ActiveLOW JITTER, 2-INPUT SELECTABLE 1:4 UNIVERSAL-TO-LVDS BUFFER
Deep-Dive with AI
Search across all available documentation for this part.
CDCLVD1204RGTR
ActiveLOW JITTER, 2-INPUT SELECTABLE 1:4 UNIVERSAL-TO-LVDS BUFFER
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | CDCLVD1204RGTR |
|---|---|
| Differential - Input:Output [custom] | True |
| Differential - Input:Output [custom] | True |
| Frequency - Max [Max] | 800 MHz |
| Input | LVDS, LVCMOS, LVPECL |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output | LVDS |
| Package / Case | 16-VFQFN Exposed Pad |
| Ratio - Input:Output [custom] | 2:4 |
| Supplier Device Package | 16-VQFN (3x3) |
| Type | Fanout Buffer (Distribution), Multiplexer |
| Voltage - Supply [Max] | 2.625 V |
| Voltage - Supply [Min] | 2.375 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 6.35 | |
| 10 | $ 5.74 | |||
| 25 | $ 5.47 | |||
| 100 | $ 4.75 | |||
| 250 | $ 4.54 | |||
| 500 | $ 4.14 | |||
| 1000 | $ 3.60 | |||
| Digi-Reel® | 1 | $ 6.35 | ||
| 10 | $ 5.74 | |||
| 25 | $ 5.47 | |||
| 100 | $ 4.75 | |||
| 250 | $ 4.54 | |||
| 500 | $ 4.14 | |||
| 1000 | $ 3.60 | |||
| Tape & Reel (TR) | 3000 | $ 3.47 | ||
| Texas Instruments | LARGE T&R | 1 | $ 4.86 | |
| 100 | $ 3.96 | |||
| 250 | $ 3.12 | |||
| 1000 | $ 2.64 | |||
Description
General part information
CDCLVD1204 Series
The CDCLVD1204 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 pairs of differential LVDS clock outputs (OUT0 through OUT3) with minimum skew for clock distribution. The CDCLVD1204 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS.
The CDCLVD1204 is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage, VAC_REF, must be applied to the unused negative input pin.
The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static). The part supports a fail safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.
Documents
Technical documentation and resources
