Specification	CD40192BE

Count Rate	5.5 MHz
Direction	Up, Down
Logic Type	Counter, Decade
Mounting Type	Through Hole
Number of Bits per Element	4
Number of Elements	1
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-55 °C
Package / Case	0.3 in
Package / Case	16-DIP
Package / Case	7.62 mm
Reset	Asynchronous
Supplier Device Package	16-PDIP
Timing	Synchronous
Trigger Type	Positive Edge
Voltage - Supply [Max]	18 V
Voltage - Supply [Min]	3 V

CD40192B Series

CMOS Presettable BCD Up/Down Counter (Dual Clock with Reset)

Part	Operating Temperature [Min]	Operating Temperature [Max]	Voltage - Supply [Max]	Voltage - Supply [Min]	Supplier Device Package	Number of Bits per Element	Logic Type	Number of Elements	Timing	Count Rate	Mounting Type	Package / Case	Package / Case	Package / Case	Direction	Reset	Trigger Type	Package / Case [x]	Package / Case [y]
Texas Instruments CD40192BE	-55 °C	125 °C	18 V	3 V	16-PDIP	4	Counter Decade	1	Synchronous	5.5 MHz	Through Hole	0.3 in	16-DIP	7.62 mm	Down Up	Asynchronous	Positive Edge
Texas Instruments CD40192BPWR	-55 °C	125 °C	18 V	3 V	16-TSSOP	4	Counter Decade	1	Synchronous	5.5 MHz	Surface Mount		16-TSSOP		Down Up	Asynchronous	Positive Edge	0.173 in	4.4 mm
Texas Instruments CD40192BPW	-55 °C	125 °C	18 V	3 V	16-TSSOP	4	Counter Decade	1	Synchronous	5.5 MHz	Surface Mount		16-TSSOP		Down Up	Asynchronous	Positive Edge	0.173 in	4.4 mm

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tube	1	$ 1.10
		10	$ 0.98
		25	$ 0.93
		100	$ 0.76
		250	$ 0.71
		467	$ 0.64
		500	$ 0.63
		1000	$ 0.50
		2500	$ 0.47
		5000	$ 0.44
Newark	Each	1	$ 1.46
		10	$ 1.34
		100	$ 1.22
		500	$ 1.15
		1000	$ 1.10
		2500	$ 1.04
		5000	$ 1.02
Texas Instruments	TUBE	1	$ 0.90
		100	$ 0.69
		250	$ 0.51
		1000	$ 0.36

Description

General part information

CD40192B Series

CD40192b Presettable BCD Up/Down Counter and the CD40193B Presettable Binary Up/Down Counter each consist of 4 synchronously clocked, gated "D" type flip-flops connected as a counter. The inputs consist of 4 individual jam lines, a PRESET\ ENABLE\ control, individual CLOCK UP and CLOCK DOWN signals and a master RESET. Four buffered Q signal outputs as well as CARRY\ and BORROW\ outputs for multiple-stage counting schemes are provided.

The counter is cleared so that all outputs are in a low state by a high on the RESET line. A RESET is accomplished asynchronously with the clock. Each output is individually programmable asynchronously with the clock to the level on the corresponding jam input when the PRESET\ ENABLE\ control is low.

The counter counts up one count on the positive clock edge of the CLOCK UP signal provided the CLOCK DOWN line is high. The counter counts down on count on the positive clock edge of the CLOCK DOWN signal provided the CLOCK UP line is high.

Documents

Technical documentation and resources

CD40192B, CD40193B TYPES datasheet (Rev. B)

Data sheet