Specification	ADC08D502CIYB/NOPB

Architecture	Folding Interpolating
Configuration	MUX-S/H-ADC
Data Interface	LVDS - Parallel
Features	Simultaneous Sampling
Input Type	Differential
Mounting Type	Surface Mount
Number of A/D Converters	2
Number of Bits	8
Number of Inputs	2
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Ratio - S/H:ADC	1:1
Reference Type	Internal
Sampling Rate (Per Second)	500 M
Supplier Device Package	128-HLQFP (20x20)
Voltage - Supply, Analog [Max]	2 V
Voltage - Supply, Analog [Min]	1.8 V
Voltage - Supply, Digital [Max]	2 V
Voltage - Supply, Digital [Min]	1.8 V

ADC08D502 Series

Dual-Channel, 8-Bit, 500-MSPS Analog-to-Digital Converter (ADC)

Part	Voltage - Supply, Digital [Max]	Voltage - Supply, Digital [Min]	Input Type	Features	Sampling Rate (Per Second)	Voltage - Supply, Analog [Min]	Voltage - Supply, Analog [Max]	Reference Type	Mounting Type	Configuration	Data Interface	Architecture	Supplier Device Package	Operating Temperature [Max]	Operating Temperature [Min]	Number of A/D Converters	Number of Inputs	Number of Bits	Ratio - S/H:ADC
Texas Instruments ADC08D502CIYB/NOPB	2 V	1.8 V	Differential	Simultaneous Sampling	500 M	1.8 V	2 V	Internal	Surface Mount	MUX-S/H-ADC	LVDS - Parallel	Folding Interpolating	128-HLQFP (20x20)	85 °C	-40 °C	2	2	8	1:1

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tray	60	$ 82.49
Texas Instruments	JEDEC TRAY (10+1)	1	$ 75.96
		100	$ 73.67
		250	$ 61.34
		1000	$ 57.11

Description

General part information

ADC08D502 Series

The ADC08D502 is a dual, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 500 MSPS. Consuming a typical 1.4 Watts at 500 MSPS from a single 1.9 Volt supply, this device is specified to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 7.5 ENOB with a 250 MHz input signal and a 500 MHz sample rate while providing a 10-18B.E.R. Output formatting is offset binary and the LVDS digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V.

Each converter has a 1:2 demultiplexer that feeds two LVDS buses and reduces the output data rate on each bus to half the sampling rate.

The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad HLQFP and operates over the Industrial (-40°C ≤ TA≤ +85°C) temperature range.

Documents

Technical documentation and resources

ADC08D502 Hi Perf, Low Power, Dual 8-Bit, 500 MSPS A/D Conv datasheet (Rev. A)

Data sheet