
MC74LCX74DG
ActiveFLIP-FLOP, COMPLEMENTARY, DIFFERENTIAL, POSITIVE EDGE, 74LCX74, D, 7 NS, 150 MHZ, 24 MA, SOIC
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MC74LCX74DG
ActiveFLIP-FLOP, COMPLEMENTARY, DIFFERENTIAL, POSITIVE EDGE, 74LCX74, D, 7 NS, 150 MHZ, 24 MA, SOIC
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Technical Specifications
Parameters and characteristics for this part
| Specification | MC74LCX74DG |
|---|---|
| Clock Frequency | 150 MHz |
| Current - Output High, Low | 24 mA |
| Current - Quiescent (Iq) | 10 µA |
| Function | Reset, Set(Preset) |
| Input Capacitance | 7 pF |
| Max Propagation Delay @ V, Max CL | 7 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 1 |
| Number of Elements | 2 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Complementary |
| Package / Case | 14-SOIC |
| Package / Case [x] | 0.154 in |
| Package / Case [y] | 3.9 mm |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 1 | $ 0.82 | |
| 10 | $ 0.49 | |||
| 55 | $ 0.35 | |||
| 110 | $ 0.31 | |||
| 275 | $ 0.27 | |||
| 550 | $ 0.24 | |||
| 1045 | $ 0.24 | |||
| Newark | Each | 1000 | $ 0.24 | |
| 2500 | $ 0.19 | |||
| 10000 | $ 0.18 | |||
| ON Semiconductor | N/A | 1 | $ 0.19 | |
Description
General part information
MC74LCX74 Series
The MC74LCX74 is a high performance, dual D-type flip-flop with asynchronous clear and set inputs and complementary (O, Obar) outputs. Itoperates from a 2.7 to 3.6V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A V Ispecification of 5.5V allows MC74LCX74 inputs to be safely driven from5V devices.The MC74LCX74 consists of 2 edge-triggered flip-flops with individual D-type inputs. The flip-flop will store the state of individual D inputs, that meet the setup and hold time requirements, on the LOW-to-HIGH Clock (CP) transition.
Documents
Technical documentation and resources