Specification	SN65LVCP1412RLHR

Data Rate (Max)	14.2 Gbps
Delay Time	65 ps
Input	CML
Mounting Type	Surface Mount
Number of Channels [custom]	2
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output	CML
Package / Case	24-WFQFN Exposed Pad
Signal Conditioning	Output Pre-Emphasis, Input Equalization
Supplier Device Package	24-WQFN (4x5)
Type	ReDriver, Buffer
Voltage - Supply [Max]	3.465 V
Voltage - Supply [Min]	2.375 V

SN65LVCP1412 Series

14.2-Gbps dual channel, dual mode linear equalizer

Part	Number of Channels [custom]	Signal Conditioning	Type	Input	Delay Time	Output	Supplier Device Package	Mounting Type	Data Rate (Max)	Package / Case	Voltage - Supply [Min]	Voltage - Supply [Max]	Operating Temperature [Max]	Operating Temperature [Min]
Texas Instruments SN65LVCP1412RLHT	2	Input Equalization Output Pre-Emphasis	Buffer ReDriver	CML	65 ps	CML	24-WQFN (4x5)	Surface Mount	14.2 Gbps	24-WFQFN Exposed Pad	2.375 V	3.465 V	85 °C	-40 °C
Texas Instruments SN65LVCP1412RLHR	2	Input Equalization Output Pre-Emphasis	Buffer ReDriver	CML	65 ps	CML	24-WQFN (4x5)	Surface Mount	14.2 Gbps	24-WFQFN Exposed Pad	2.375 V	3.465 V	85 °C	-40 °C

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Texas Instruments	LARGE T&R	1	$ 10.96
		100	$ 9.57
		250	$ 7.38
		1000	$ 6.60

Description

General part information

SN65LVCP1412 Series

The SN65LVCP1412 is an asynchronous, protocol-agnostic, low latency, two-channel linear equalizer optimized for use up to 14.2Gbps and compensates for losses in backplane or active cable applications. The architecture of SN65LVCP1412 is designed to work with an ASIC or a FPGA with digital equalization employing Decision Feedback Equalizers (DFE). SN65LVCP1412 linear equalizer preserves the shape of the transmitted signal ensuring optimum DFE performance. SN65LVCP1412 provides a low power solution while at the same time extending the effectiveness of DFE.

SN65LVCP1412 is configurable via I2C or GPIO interface. Using the I2C interface of the SN65LVCP1412 enables the user to control independently the Equalization, Path Gain, and Output Dynamic Range for each individual channel. In GPIO mode, Equalization, Path Gain, and Output Dynamic Range can be set for all channels using the GPIO Input pins.

SN65LVCP1412 outputs can be disabled independently via I2C.

Documents

Technical documentation and resources

14.2-GBPS DUAL CHANNEL, DUAL MODE LINEAR EQUALIZER datasheet

Data sheet