SN74LS73AN
ActiveFLIP FLOP JK-MASTER-SLAVE TYPE NEG-EDGE 2-ELEMENT 14-PIN PDIP TUBE
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SN74LS73AN
ActiveFLIP FLOP JK-MASTER-SLAVE TYPE NEG-EDGE 2-ELEMENT 14-PIN PDIP TUBE
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Technical Specifications
Parameters and characteristics for this part
| Specification | SN74LS73AN |
|---|---|
| Clock Frequency | 45 MHz |
| Current - Output High, Low [custom] | 400 µA |
| Current - Output High, Low [custom] | 8 mA |
| Current - Quiescent (Iq) | 6 mA |
| Max Propagation Delay @ V, Max CL | 20 ns |
| Mounting Type | Through Hole |
| Number of Bits per Element | 1 |
| Number of Elements | 2 |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Output Type | Complementary |
| Package / Case | 14-DIP |
| Package / Case [x] | 0.3 " |
| Package / Case [y] | 7.62 mm |
| Trigger Type | Negative Edge |
| Type | JK Type |
| Voltage - Supply [Max] | 5.25 V |
| Voltage - Supply [Min] | 4.75 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Arrow | N/A | 25 | $ 1.19 | |
| 100 | $ 1.12 | |||
| 250 | $ 1.11 | |||
| Digikey | Tube | 1 | $ 1.78 | |
| 10 | $ 1.60 | |||
| 25 | $ 1.51 | |||
| 100 | $ 1.28 | |||
| 250 | $ 1.20 | |||
| 500 | $ 1.06 | |||
| Newark | Each | 1 | $ 3.28 | |
| 10 | $ 3.04 | |||
| 25 | $ 2.84 | |||
| 50 | $ 2.70 | |||
| 100 | $ 2.55 | |||
| 250 | $ 2.42 | |||
| Texas Instruments | TUBE | 1 | $ 2.09 | |
| 100 | $ 1.72 | |||
| 250 | $ 1.24 | |||
| 1000 | $ 0.93 | |||
Description
General part information
SN74LS73A Series
The '73, and 'H73, contain two independent J-K flip-flops with individual J-K, clock, and direct clear inputs. The '73, and 'H73, are positive pulse-triggered flip-flops. J-K input is loaded into the master while the clock is high and transferred to the slave on the high-to-low transition. For these devices the J and K inputs must be stable while the clock is high.
The 'LS73A contains two independent negative-edge-triggered flip-flops. The J and K inputs must be stable one setup time prior to the high-to-low clock transition for predictable operation. When the clear is low, it overrides the clock and data inputs forcing the Q output low and the Q\ output high.
The SN5473, SN54H73, and the SN54LS73A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN7473, and the SN74LS73A are characterized for operation from 0°C to 70°C.
Documents
Technical documentation and resources
