CD74HCT597M
ObsoleteHIGH SPEED CMOS LOGIC 8-BIT SHIFT REGISTER WITH INPUT STORAGE
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CD74HCT597M
ObsoleteHIGH SPEED CMOS LOGIC 8-BIT SHIFT REGISTER WITH INPUT STORAGE
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Technical Specifications
Parameters and characteristics for this part
| Specification | CD74HCT597M |
|---|---|
| Function | Parallel to Serial |
| Logic Type | Shift Register |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 8 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Output Type | Push-Pull |
| Package / Case | 16-SOIC |
| Package / Case [x] | 0.154 in |
| Package / Case [y] | 3.9 mm |
| Supplier Device Package | 16-SOIC |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 1 | $ 1.57 | |
| 10 | $ 1.41 | |||
| 40 | $ 1.33 | |||
| 120 | $ 1.13 | |||
| 280 | $ 1.06 | |||
| 395 | $ 0.76 | |||
| Texas Instruments | TUBE | 1 | $ 1.30 | |
| 100 | $ 1.00 | |||
| 250 | $ 0.74 | |||
| 1000 | $ 0.53 | |||
Description
General part information
CD74HCT597 Series
The ’HC597 and CD74HCT597 are high-speed silicon gate CMOS devices that are pin compatible with the LSTTL 597 devices. Each device consists of an 8-flip-flop input register and an 8-bit parallel-in/serial-in, serial-out shift register. Each register is controlled by its own clock. A "low" on the parallel load input (PL\) shifts parallel stored data asynchronously into the shift register. A "low" master input (MR\) clears the shift register. Serial input data can also be synchronously shifted through the shift register when PL\ is high.
The ’HC597 and CD74HCT597 are high-speed silicon gate CMOS devices that are pin compatible with the LSTTL 597 devices. Each device consists of an 8-flip-flop input register and an 8-bit parallel-in/serial-in, serial-out shift register. Each register is controlled by its own clock. A "low" on the parallel load input (PL\) shifts parallel stored data asynchronously into the shift register. A "low" master input (MR\) clears the shift register. Serial input data can also be synchronously shifted through the shift register when PL\ is high.
Documents
Technical documentation and resources
