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SOIC (D)
Integrated Circuits (ICs)

CD74HCT4060M

Obsolete
Texas Instruments

HIGH SPEED CMOS LOGIC 14-STAGE BINARY COUNTER WITH OSCILLATOR

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SOIC (D)
Integrated Circuits (ICs)

CD74HCT4060M

Obsolete
Texas Instruments

HIGH SPEED CMOS LOGIC 14-STAGE BINARY COUNTER WITH OSCILLATOR

Technical Specifications

Parameters and characteristics for this part

SpecificationCD74HCT4060M
Count Rate30 MHz
DirectionUp
Logic TypeBinary Counter
Mounting TypeSurface Mount
Number of Bits per Element [custom]14
Number of Elements1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Package / Case16-SOIC
Package / Case [x]0.154 in
Package / Case [y]3.9 mm
ResetAsynchronous
Supplier Device Package16-SOIC
Trigger TypeNegative Edge
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
ArrowN/A 1$ 0.05
DigikeyTube 1$ 1.49
10$ 1.33
40$ 1.26
120$ 1.04
280$ 0.97
466$ 0.64
Texas InstrumentsTUBE 1$ 1.28
100$ 0.87
250$ 0.67
1000$ 0.45

Description

General part information

CD74HCT4060 Series

The ’HC4060 and ’HCT4060 each consist of an oscillator section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC or crystal oscillator circuits. A Master Reset input is provided which resets the counter to the all-0’s state and disables the oscillator. A high level on the MR line accomplishes the reset function. All counter stages are master-slave flip-flops. The state of the counter is advanced one step in binary order on the negative transition ofO). All inputs and outputs are buffered. Schmitt trigger action on the input-pulse-line permits unlimited rise and fall times.

In order to achieve a symmetrical waveform in the oscillator section the HCT4060 input pulse switch points are the same as in the HC4060; only the MR input in the HCT4060 has TTL switching levels.

The ’HC4060 and ’HCT4060 each consist of an oscillator section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC or crystal oscillator circuits. A Master Reset input is provided which resets the counter to the all-0’s state and disables the oscillator. A high level on the MR line accomplishes the reset function. All counter stages are master-slave flip-flops. The state of the counter is advanced one step in binary order on the negative transition ofO). All inputs and outputs are buffered. Schmitt trigger action on the input-pulse-line permits unlimited rise and fall times.