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SOIC (D)
Integrated Circuits (ICs)

NA555DR

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Texas Instruments

STANDARD TIMER SINGLE -40°C 105°C 8-PIN SOIC T/R

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SOIC (D)
Integrated Circuits (ICs)

NA555DR

Active
Texas Instruments

STANDARD TIMER SINGLE -40°C 105°C 8-PIN SOIC T/R

Technical Specifications

Parameters and characteristics for this part

SpecificationNA555DR
Current - Supply10 mA
Frequency100 kHz
Mounting TypeSurface Mount
Operating Temperature [Max]105 ░C
Operating Temperature [Min]-40 °C
Package / Case8-SOIC
Package / Case [x]0.154 in
Package / Case [y]3.9 mm
Supplier Device Package8-SOIC
Type555 Type, Timer/Oscillator (Single)
Voltage - Supply [Max]16 V
Voltage - Supply [Min]4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
ArrowN/A 5$ 0.25
DigikeyCut Tape (CT) 1$ 0.42
10$ 0.34
25$ 0.31
100$ 0.23
250$ 0.21
500$ 0.17
1000$ 0.13
Digi-Reel® 1$ 0.42
10$ 0.34
25$ 0.31
100$ 0.23
250$ 0.21
500$ 0.17
1000$ 0.13
Tape & Reel (TR) 2500$ 0.12
5000$ 0.11
12500$ 0.11
25000$ 0.10
62500$ 0.09
Texas InstrumentsLARGE T&R 1$ 0.17
100$ 0.12
250$ 0.09
1000$ 0.06

Description

General part information

NA555 Series

The Nx555 and Sx555 devices are precision timing circuits capable of producing accurate time delays or oscillation. In time-delay or monostable operating modes, the timed interval is controlled by a single external resistor and capacitor network. In the astable mode of operation, the frequency and duty cycle are controlled independently with two external resistors and a single external capacitor.

Each timer has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage pin (CONT). When the trigger input (TRIG) is less than the trigger level, the flip-flop is set and the output goes high. If TRIG is greater than the trigger level and the threshold input (THRES) is greater than the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) overrides all other inputs and is used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge pin (DISCH) and the ground pin (GND). Tie all unused inputs to an appropriate logic level to prevent false triggering

The output circuit is capable of sinking or sourcing current up to 200mA. Operation is specified for supplies of 5V to 15V. With a 5V supply, output levels are compatible with TTL inputs.