SN74AUC16374DGVR
Active16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
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SN74AUC16374DGVR
Active16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74AUC16374DGVR |
|---|---|
| Clock Frequency | 250 MHz |
| Current - Output High, Low [custom] | 9 mA |
| Current - Output High, Low [custom] | 9 mA |
| Current - Quiescent (Iq) | 20 çA |
| Function | Standard |
| Input Capacitance | 3 pF |
| Max Propagation Delay @ V, Max CL | 2.2 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 8 |
| Number of Elements | 2 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Tri-State, Non-Inverted |
| Package / Case | 0.173 in, 4.4 mm |
| Package / Case | 48-TFSOP |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 2.7 V |
| Voltage - Supply [Min] | 0.8 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 2.75 | |
| 10 | $ 2.47 | |||
| 25 | $ 2.33 | |||
| 100 | $ 1.99 | |||
| 250 | $ 1.87 | |||
| 500 | $ 1.63 | |||
| 1000 | $ 1.35 | |||
| Digi-Reel® | 1 | $ 2.75 | ||
| 10 | $ 2.47 | |||
| 25 | $ 2.33 | |||
| 100 | $ 1.99 | |||
| 250 | $ 1.87 | |||
| 500 | $ 1.63 | |||
| 1000 | $ 1.35 | |||
| Tape & Reel (TR) | 2000 | $ 1.26 | ||
| 6000 | $ 1.21 | |||
| Texas Instruments | LARGE T&R | 1 | $ 2.07 | |
| 100 | $ 1.71 | |||
| 250 | $ 1.23 | |||
| 1000 | $ 0.92 | |||
Description
General part information
SN74AUC16374 Series
This 16-bit edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCCoperation.
The SN74AUC16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
Documents
Technical documentation and resources
