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Technical Specifications
Parameters and characteristics for this part
| Specification | SN74F174ANSR |
|---|---|
| Clock Frequency | 140 MHz |
| Current - Output High, Low [custom] | 1 mA |
| Current - Output High, Low [custom] | 20 mA |
| Current - Quiescent (Iq) | 45 mA |
| Max Propagation Delay @ V, Max CL | 10 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 6 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Output Type | Non-Inverted |
| Package / Case | 0.209 " |
| Package / Case | 16-SOIC |
| Package / Case | 5.3 mm |
| Supplier Device Package | 16-SO |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
SN74F174A Series
This monolithic, positive-edge-triggered flip-flop utilizes TTL circuitry to implement D-type flip-flop logic with a direct clear () input. Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
The SN74F174A is characterized for operation from 0°C to 70°C.
This monolithic, positive-edge-triggered flip-flop utilizes TTL circuitry to implement D-type flip-flop logic with a direct clear () input. Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output.
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