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20-SOIC
Integrated Circuits (ICs)

CY74FCT2373CTSOC

Active
Texas Instruments

OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS AND SERIES DAMPING RESISTORS

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Search across all available documentation for this part.

DocumentsUnderstanding and Interpreting Standard-Logic Data Sheets (Rev. C)CYFCT Parameter Measurement Information+7
20-SOIC
Integrated Circuits (ICs)

CY74FCT2373CTSOC

Active
Texas Instruments

OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS AND SERIES DAMPING RESISTORS

Deep-Dive with AI

DocumentsUnderstanding and Interpreting Standard-Logic Data Sheets (Rev. C)CYFCT Parameter Measurement Information+7

Technical Specifications

Parameters and characteristics for this part

SpecificationCY74FCT2373CTSOC
Circuit [custom]8
Circuit [custom]8
Current - Output High, Low [custom]15 mA
Current - Output High, Low [custom]12 mA
Independent Circuits1
Logic TypeD-Type Transparent Latch
Mounting TypeSurface Mount
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Output TypeTri-State
Package / Case20-SOIC
Package / Case [y]0.295 in
Package / Case [y]7.5 mm
Supplier Device Package20-SOIC
Voltage - Supply [Max]5.25 V
Voltage - Supply [Min]4.75 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 1$ 0.91
10$ 0.80
25$ 0.75
100$ 0.61
250$ 0.57
500$ 0.48
1000$ 0.39
2500$ 0.35
5000$ 0.33
Texas InstrumentsTUBE 1$ 0.59
100$ 0.45
250$ 0.33
1000$ 0.24

Description

General part information

CY74FCT2373T Series

The CY74FCT2373T is an 8-bit, high-speed CMOS, TTL-compatible buffered latch with 3-state outputs that is ideal for driving high-capacitance loads, such as memory and address buffers. On-chip 25-termination resistors at the outputs reduce system noise caused by reflections. The CY74FCT2373T can replace the CY74FCT373T to reduce noise in an existing design.

When the latch-enable (LE) input is high, the flip-flops appear transparent to the data. Data that meets the required setup times are latched when LE transitions from high to low. Data appears on the bus when the output-enable (OE\) input is low. When OE\ is high, the bus output is in the high-impedance state. In this mode, data can be entered into the latches.

This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.