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Integrated Circuits (ICs)

NC7SP74K8X

Obsolete
ON Semiconductor

TINYLOGIC ULP D-TYPE FLIP-FLOP WITH PRESET AND CLEAR

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DocumentsDatasheet
US8
Integrated Circuits (ICs)

NC7SP74K8X

Obsolete
ON Semiconductor

TINYLOGIC ULP D-TYPE FLIP-FLOP WITH PRESET AND CLEAR

Deep-Dive with AI

DocumentsDatasheet

Technical Specifications

Parameters and characteristics for this part

SpecificationNC7SP74K8X
Clock Frequency150 MHz
Current - Output High, Low [custom]2.6 mA
Current - Output High, Low [custom]2.6 mA
Current - Quiescent (Iq)900 nA
FunctionReset, Set(Preset)
Input Capacitance2 pF
Max Propagation Delay @ V, Max CL8 ns
Mounting TypeSurface Mount
Number of Bits per Element1
Number of Elements1
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Output TypeComplementary
Package / Case8-VFSOP
Package / Case [y]2.3 mm
Package / Case [y]0.091 in
Supplier Device PackageUS8
Trigger TypePositive Edge
TypeD-Type
Voltage - Supply [Max]3.6 V
Voltage - Supply [Min]0.9 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 0.83
10$ 0.48
25$ 0.40
100$ 0.30
250$ 0.26
500$ 0.23
1000$ 0.21
Digi-Reel® 1$ 0.83
10$ 0.48
25$ 0.40
100$ 0.30
250$ 0.26
500$ 0.23
1000$ 0.21
Tape & Reel (TR) 3000$ 0.17
6000$ 0.15
15000$ 0.15
30000$ 0.14

Description

General part information

NC7SP74 Series

The NC7SP74 is a single D-type CMOS Flip-Flop with preset and clear from ON Semiconductor's Ultra Low Power (ULP) Series of TinyLogic®. Ideal for applications where battery life is critical, this product is designed for ultra low power consumption within the VCCoperating range of 0.9V to 3.6V. The internal circuit is composed of a minimum of inverter stages including the output buffer, to enable ultra low static and dynamic power. The NC7SP74, for lower drive requirements, is uniquely designed for optimized power and speed, and is fabricated with an advanced CMOS technology to achieve best in class speed operation while maintaining extremely low CMOS power dissipation. The signal level applied to the D input is transferred to the Q output during the positive going transition of the CLK pulse.

Documents

Technical documentation and resources