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Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | NS16C2552TVA/NOPB |
|---|---|
| Data Rate (Max) [Max] | 5 Mbps |
| FIFO's | 16 Byte |
| Mounting Type | Surface Mount |
| Number of Channels | 2 |
| Package / Case | 44-LCC (J-Lead) |
| Supplier Device Package | 44-PLCC |
| Supplier Device Package [x] | 16.58 |
| Supplier Device Package [y] | 16.58 |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 2.97 V |
| With Auto Flow Control | True |
| With IrDA Encoder/Decoder | True |
| With Modem Control | True |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 1 | $ 11.12 | |
| 10 | $ 10.22 | |||
| 25 | $ 9.80 | |||
| 100 | $ 8.63 | |||
| 250 | $ 8.21 | |||
| 500 | $ 7.68 | |||
| 1000 | $ 7.04 | |||
Description
General part information
NS16C2552 Series
The NS16C2552 and NS16C2752 are dual channel Universal Asynchronous Receiver/Transmitter (DUART). The footprint and the functions are compatible to the PC16552D, while new features are added to the UART device. These features include low voltage support, 5V tolerant inputs, enhanced features, enhanced register set, and higher data rate.
The two serial channels are completely independent of each other, except for a common CPU interface and crystal input. On power-up both channels are functionally identical to the PC16552D. Each channel can operate with on-chip transmitter and receiver FIFO’s (in FIFO mode).
In the FIFO mode each channel is capable of buffering 16 bytes (for NS16C2552) or 64 bytes (for NS16C2752) of data in both the transmitter and receiver. The receiver FIFO also has additional 3 bits of error data per location. All FIFO control logic is on-chip to minimize system software overhead and maximize system efficiency.
Documents
Technical documentation and resources
No documents available