Integrated Circuits (ICs)

74ALVTH16601DLG4

Unknown

Texas Instruments

BUS XCVR SINGLE 18-CH 3-ST 56-PIN SSOP TUBE

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Integrated Circuits (ICs)

74ALVTH16601DLG4

Unknown

Texas Instruments

BUS XCVR SINGLE 18-CH 3-ST 56-PIN SSOP TUBE

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Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	74ALVTH16601DLG4

Current - Output High, Low [custom]	8 mA
Current - Output High, Low [custom]	8 mA
Mounting Type	Surface Mount
Number of Circuits	18 Bit
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Package / Case	0.295 in
Package / Case	56-BSSOP
Package / Case	7.5 mm
Supplier Device Package	56-SSOP
Voltage - Supply [Max]	2.7 V
Voltage - Supply [Min]	2.3 V

SN74ALVTH16601 Series

2.5-V/3.3-V 18-bit universal bus transceiver with 3-state outputs

Part	Voltage - Supply [Max]	Voltage - Supply [Min]	Mounting Type	Supplier Device Package	Operating Temperature [Max]	Operating Temperature [Min]	Package / Case	Package / Case	Package / Case	Number of Circuits	Current - Output High, Low [custom]	Current - Output High, Low [custom]
Texas Instruments 74ALVTH16601DLG4	2.7 V	2.3 V	Surface Mount	56-SSOP	85 °C	-40 °C	0.295 in	56-BSSOP	7.5 mm	18 Bit	8 mA	8 mA
Texas Instruments SN74ALVTH16601DLR	2.7 V	2.3 V	Surface Mount	56-SSOP	85 °C	-40 °C	0.295 in	56-BSSOP	7.5 mm	18 Bit	8 mA	8 mA
Texas Instruments SN74ALVTH16601GR	2.7 V	2.3 V	Surface Mount	56-TSSOP	85 °C	-40 °C	0.24 in	56-TFSOP	6.1 mm	18 Bit	8 mA	8 mA

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Description

General part information

SN74ALVTH16601 Series

The 'ALVTH16601 devices are 18-bit universal bus transceivers designed for 2.5-V or 3.3-V VCCoperation, but with the capability to provide a TTL interface to a 5-V system environment.

The devices combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.

Data flow in each direction is controlled by output-enable (OEAB\ and OEBA\), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB\ and CLKENBA\) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the low-to-high transition of CLKAB. Output enable OEAB\ is active low. When OEAB\ is low, the outputs are active. When OEAB\ is high, the outputs are in the high-impedance state.

Documents

Technical documentation and resources

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