
CD54ACT139F3A
ActiveCDIP-16 SIGNAL SWITCHES, MULTIPLEXERS, DECODERS ROHS
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CD54ACT139F3A
ActiveCDIP-16 SIGNAL SWITCHES, MULTIPLEXERS, DECODERS ROHS
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | CD54ACT139F3A |
|---|---|
| null | |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Bulk | 28 | $ 11.06 | |
| LCSC | Piece | 1 | $ 25.75 | |
| 200 | $ 9.96 | |||
| 500 | $ 9.61 | |||
| 1000 | $ 9.44 | |||
| Texas Instruments | TUBE | 1 | $ 14.62 | |
| 100 | $ 12.77 | |||
| 250 | $ 9.85 | |||
| 1000 | $ 8.81 | |||
Description
General part information
CD54ACT139 Series
The ’ACT139 devices are dual 2-line to 4-line decoders/demultiplexers designed for 4.5-V to 5.5-V VCCoperation. These devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.
The active-low enable (G)\ input can be used as a data line in demultiplexing applications. These decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit.
The ’ACT139 devices are dual 2-line to 4-line decoders/demultiplexers designed for 4.5-V to 5.5-V VCCoperation. These devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.
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