DRA821U2CGBALMR
ActiveDUAL ARM CORTEX-A72, QUAD CORTEX-R5F, 4-PORT ETHERNET SWITCH, AND A PCIE CONTROLLER
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DRA821U2CGBALMR
ActiveDUAL ARM CORTEX-A72, QUAD CORTEX-R5F, 4-PORT ETHERNET SWITCH, AND A PCIE CONTROLLER
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Technical Specifications
Parameters and characteristics for this part
| Specification | DRA821U2CGBALMR |
|---|---|
| Architecture | MPU, MCU |
| Connectivity | I2C, I3C, UART, MMC/SD/SDIO, SPI, Ethernet, USB, MCAN |
| Core Processor | ARM® Cortex®-A72, ARM® Cortex®-R5F |
| Number of I/O | 141 |
| Operating Temperature [custom] | -40 °C, 105 °C |
| Package / Case | FCBGA, 433-BFBGA |
| Peripherals | WDT, PWM, DMA |
| RAM Size | 1.5 MB |
| Speed | 500 MHz |
| Speed | 750 MHz |
| Supplier Device Package | 433-FCBGA (17.2x17.2) |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tape & Reel (TR) | 500 | $ 24.89 | |
| Texas Instruments | LARGE T&R | 1 | $ 27.33 | |
| 100 | $ 24.29 | |||
| 250 | $ 19.97 | |||
| 1000 | $ 17.86 | |||
Description
General part information
DRA821U Series
Jacinto™ DRA821x processors, based on the Armv8 64-bit architecture, are optimized for gateway systems with cloud connectivity. The System-on-Chip (SoC) design reduces system-level costs and complexity through integration—notably, a system MCU, functional safety and security features, and an Ethernet switch for high-speed communication. Integrated diagnostics and functional safety features are targeted to ASIL-D and SIL 3 certification requirements. Real-time control and low-latency communication are enabled by a PCIe controller and a TSN capable Gigabit Ethernet switch.
Up to four general-purpose Arm® Cortex®-R5F subsystems can handle low-level, timing-critical processing tasks and leave the Arm® Cortex®-A72 core unencumbered for advanced and cloud-based applications.
Jacinto DRA821x processors also include the concept of the Extended MCU (eMCU) domain. This domain is a subset of the processors and peripherals on the main domain targeted at higher functional safety enablement, such as ASIL-D/SIL-3. The functional block diagram highlights which IP are included in the eMCU. For more details about eMCU and functional safety, see the DRA821 Safety Manual Processors Texas Instruments Jacinto™ 7 Family of Products (SPRUIX4).
Documents
Technical documentation and resources