DS90UH928QSQX/NOPB
Unknown5MHZ - 85MHZ 24-BIT COLOR FPD-LINK III TO FPD-LINK DESERIALIZER WITH HDCP
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DS90UH928QSQX/NOPB
Unknown5MHZ - 85MHZ 24-BIT COLOR FPD-LINK III TO FPD-LINK DESERIALIZER WITH HDCP
Technical Specifications
Parameters and characteristics for this part
| Specification | DS90UH928QSQX/NOPB |
|---|---|
| Data Rate | 2.975 Gbps |
| Function | Deserializer |
| Grade | Automotive |
| Input Type | FPD-Link III, LVDS |
| Mounting Type | Surface Mount |
| Number of Inputs | 1 |
| Number of Outputs | 5 |
| Operating Temperature [Max] | 105 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | LVCMOS |
| Package / Case | 48-WFQFN Exposed Pad |
| Qualification | AEC-Q100 |
| Supplier Device Package | 48-WQFN (7x7) |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 3 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tape & Reel (TR) | 2500 | $ 7.62 | |
| Texas Instruments | LARGE T&R | 1 | $ 9.79 | |
| 100 | $ 8.55 | |||
| 250 | $ 6.59 | |||
| 1000 | $ 5.90 | |||
Description
General part information
DS90UH928Q-Q1 Series
The DS90UH928Q-Q1 deserializer, in conjunction with a DS90UH925Q-Q1 or DS90UH927Q-Q1 serializer, provides a solution for secure distribution of content-protected digital video and audio within automotive infotainment systems. The device converts a high-speed serialized interface with an embedded clock, delivered over a single signal pair (FPD-Link III), to four LVDS data/control streams, one LVDS clock pair (OpenLDI (FPD-Link)), and I2S audio data. The digital video and audio data is protected using the industry standard HDCP copy protection scheme.The serial bus scheme, FPD-Link III, supports high-speed forward channel data transmission and low-speed full duplex back channel communication over a single differential link. Consolidation of audio, video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.
Adaptive input equalization of the serial input stream provides compensation for transmission medium losses and deterministic jitter. EMI is minimized by the use of low voltage differential signaling.
The HDCP cipher engine is implemented in both the serializer and deserializer. HDCP keys are stored in on-chip memory.
Documents
Technical documentation and resources
