
SN74ABTH18502APM
ActiveSCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
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SN74ABTH18502APM
ActiveSCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
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Technical Specifications
Parameters and characteristics for this part
| Specification | SN74ABTH18502APM |
|---|---|
| Current - Output High, Low [custom] | 64 mA |
| Current - Output High, Low [custom] | 32 mA |
| Logic Type | Scan Test Universal Bus Transceiver |
| Mounting Type | Surface Mount |
| Number of Circuits | 18 Bit |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 64-LQFP |
| Supplier Device Package | 64-LQFP (10x10) |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 160 | $ 18.99 | |
| Texas Instruments | JEDEC TRAY (10+1) | 1 | $ 23.12 | |
| 100 | $ 20.20 | |||
| 250 | $ 15.57 | |||
| 1000 | $ 13.93 | |||
Description
General part information
SN74ABTH18502A Series
The 'ABTH18502A and 'ABTH182502A scan test devices with 18-bit universal bus transceivers are members of the Texas Instruments SCOPE testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
In the normal mode, these devices are 18-bit universal bus transceivers that combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. They can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE universal bus transceivers.
Data flow in each direction is controlled by output-enable (and), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A-bus data is latched while CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low, A-bus data is stored on a low-to-high transition of CLKAB. Whenis low, the B outputs are active. Whenis high, the B outputs are in the high-impedance state. B-to-A data flow is similar to A-to-B data flow but uses the, LEBA, and CLKBA inputs.
Documents
Technical documentation and resources