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128-HTQFP_4087726A
Integrated Circuits (ICs)

TSB43AB21AIPDTEP

Obsolete
Texas Instruments

ENHANCED PRODUCT INTEGRATED IEEE 1394A-2000 OHCI PHY/LINK-LAYER CONTROLLER

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128-HTQFP_4087726A
Integrated Circuits (ICs)

TSB43AB21AIPDTEP

Obsolete
Texas Instruments

ENHANCED PRODUCT INTEGRATED IEEE 1394A-2000 OHCI PHY/LINK-LAYER CONTROLLER

Technical Specifications

Parameters and characteristics for this part

SpecificationTSB43AB21AIPDTEP
FunctionPhysical Layer Controller
InterfacePCI
Operating Temperature [Max]105 ░C
Operating Temperature [Min]-40 °C
Package / Case128-TQFP
ProtocolIEEE 1394
Standardsi.Link™, IEEE 1394-1995, Firewire™, 1394a-2000, OHCI
Voltage - Supply3.3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
Texas InstrumentsJEDEC TRAY (10+1) 1$ 29.15
100$ 23.76
250$ 18.68
1000$ 15.84

Description

General part information

TSB43AB21A-EP Series

The Texas Instruments TSB43AB21A device is an integrated 1394a-2000 OHCI PHY/link-layer controller (LLC) device that is fully compliant with thePCI Local Bus Specification, thePCI Bus Power Management Interface Specification(Revision 1.1), IEEE Std 1394-1995, IEEE Std 1394a-2000, and the1394 Open Host Controller Interface Specification(Release 1.1). It is capable of transferring data between the 33-MHz PCI bus and the 1394 bus at 100M bits/s, 200M bits/s, and 400M bits/s. The TSB43AB21A device provides one 1394 port. The TSB43AB21A device also supports the IEEE Std 1394a-2000 power-down features for battery-operated applications and arbitration enhancements.

As required by the1394 Open Host Controller Interface Specification(OHCI) and IEEE Std 1394a-2000, internal control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed through configuration cycles specified by PCI, and it provides plug-and-play (PnP) compatibility. Furthermore, the TSB43AB21A device is compliant with thePCI Bus Power Management Interface Specificationas specified by thePC 2001 Design Guiderequirements. The TSB43AB21A device supports the D0, D1, D2, and D3 power states.

The TSB43AB21A design provides PCI bus master bursting, and it is capable of transferring a cacheline of data at 132M bytes/s after connection to the memory controller. Because PCI latency can be large, deep FIFOs are provided to buffer the 1394 data.