
MC100LVEL51DG
ActiveFLIP-FLOP, COMPLEMENTARY, DIFFERENTIAL, POSITIVE EDGE, D, 475 PS, 2.8 GHZ, 50 MA, SOIC
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MC100LVEL51DG
ActiveFLIP-FLOP, COMPLEMENTARY, DIFFERENTIAL, POSITIVE EDGE, D, 475 PS, 2.8 GHZ, 50 MA, SOIC
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Technical Specifications
Parameters and characteristics for this part
| Specification | MC100LVEL51DG |
|---|---|
| Clock Frequency | 2.8 GHz |
| Current - Quiescent (Iq) | 35 mA |
| Function | Reset |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 1 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Complementary |
| Package / Case | 8-SOIC |
| Package / Case [x] | 0.154 in |
| Package / Case [y] | 3.9 mm |
| Supplier Device Package | 8-SOIC |
| Trigger Type | Negative, Positive |
| Type | D-Type |
| Voltage - Supply [Max] | -3 V |
| Voltage - Supply [Min] | -3.8 V |
Pricing
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Description
General part information
MC100LVEL51 Series
The MC100LVEL51 is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 device, but operates from a 3.3V supply. With propagation delays and output transition times essentially equal to the EL51, the LVEL51 is ideally suited for those applications which require the ultimate in AC performance at 3.3V VCC.The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the LVEL51 allow the device to be used as a negative edge triggered flip-flop.The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to VEEand the CLKbar input will be biased at VCC/2.
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