Specification	CDC339DW

Differential - Input:Output	False
Frequency - Max [Max]	80 MHz
Input	TTL
Mounting Type	Surface Mount
Number of Circuits	1
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output	TTL
Package / Case	20-SOIC
Package / Case [y]	0.295 in
Package / Case [y]	7.5 mm
Ratio - Input:Output	1:8
Supplier Device Package	20-SOIC
Type	Fanout Buffer (Distribution)
Voltage - Supply [Max]	5.25 V
Voltage - Supply [Min]	4.75 V

CDC339 Series

Part	Supplier Device Package	Output	Operating Temperature [Max]	Operating Temperature [Min]	Type	Input	Mounting Type	Number of Circuits	Frequency - Max [Max]	Voltage - Supply [Min]	Voltage - Supply [Max]	Ratio - Input:Output	Package / Case	Package / Case [y]	Package / Case [y]
Texas Instruments CDC339DB	20-SSOP	TTL	85 °C	-40 °C	Fanout Buffer (Distribution)	TTL	Surface Mount	1	80 MHz	4.75 V	5.25 V	1:8	20-SSOP
Texas Instruments CDC339DBR	20-SSOP	TTL	85 °C	-40 °C	Fanout Buffer (Distribution)	TTL	Surface Mount	1	80 MHz	4.75 V	5.25 V	1:8	20-SSOP
Texas Instruments CDC339DW	20-SOIC	TTL	85 °C	-40 °C	Fanout Buffer (Distribution)	TTL	Surface Mount	1	80 MHz	4.75 V	5.25 V	1:8	20-SOIC	0.295 in	7.5 mm
Texas Instruments CDC339DWR	20-SOIC	TTL	85 °C	-40 °C	Fanout Buffer (Distribution)	TTL	Surface Mount	1	80 MHz	4.75 V	5.25 V	1:8	20-SOIC	0.295 in	7.5 mm
Texas Instruments CDC339DWG4	20-SOIC	TTL	85 °C	-40 °C	Fanout Buffer (Distribution)	TTL	Surface Mount	1	80 MHz	4.75 V	5.25 V	1:8	20-SOIC	0.295 in	7.5 mm

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tube	1	$ 12.60
		10	$ 11.58
		25	$ 11.10
		100	$ 9.78
		250	$ 9.30
		500	$ 8.70
		1000	$ 7.98
Texas Instruments	TUBE	1	$ 9.86
		100	$ 8.61
		250	$ 6.64
		1000	$ 5.94

Description

General part information

CDC339 Series

The CDC339 is a high-performance, low-skew clock driver. It is specifically designed for applications requiring synchronized output signals at both the primary clock frequency and one-half the primary clock frequency. The four Y outputs switch in phase and at the same frequency as the clock (CLK) input. The four Q outputs switch at one-half the frequency of CLK.

When the output-enable (OE) input is low and the clear (CLR) input is high, the Y outputs follow CLK and the Q outputs toggle on low-to-high transitions of CLK. TakingCLRlow asynchronously resets the Q outputs to the low level. WhenOEis high, the outputs are in the high-impedance state.

The CDC339 is characterized for operation from −40°C to 85°C.

Documents

Technical documentation and resources

CDC339 Clock Driver With 3-State Outputs datasheet (Rev. A)

Data sheet