SN74HCS273QWRKSRQ1
ActiveAUTOMOTIVE OCTAL D-TYPE FLIP-FLOPS WITH CLEAR
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SN74HCS273QWRKSRQ1
ActiveAUTOMOTIVE OCTAL D-TYPE FLIP-FLOPS WITH CLEAR
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74HCS273QWRKSRQ1 |
|---|---|
| Clock Frequency | 135 MHz |
| Current - Output High, Low [custom] | 7.8 mA |
| Current - Output High, Low [custom] | 7.8 mA |
| Current - Quiescent (Iq) | 2 µA |
| Function | Reset |
| Input Capacitance | 5 pF |
| Max Propagation Delay @ V, Max CL | 14.3 ns |
| Mounting Type | Wettable Flank, Surface Mount |
| Number of Bits per Element | 8 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Push-Pull |
| Package / Case | 20-VFQFN Exposed Pad |
| Supplier Device Package | 20-VQFN (2.5x4.5) |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 6 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 0.67 | |
| 10 | $ 0.48 | |||
| 25 | $ 0.43 | |||
| 100 | $ 0.37 | |||
| 250 | $ 0.35 | |||
| 500 | $ 0.33 | |||
| 1000 | $ 0.33 | |||
| Digi-Reel® | 1 | $ 0.67 | ||
| 10 | $ 0.48 | |||
| 25 | $ 0.43 | |||
| 100 | $ 0.37 | |||
| 250 | $ 0.35 | |||
| 500 | $ 0.33 | |||
| 1000 | $ 0.33 | |||
| Tape & Reel (TR) | 3000 | $ 0.30 | ||
| 6000 | $ 0.30 | |||
| 9000 | $ 0.29 | |||
| 15000 | $ 0.29 | |||
| 21000 | $ 0.29 | |||
| 30000 | $ 0.28 | |||
| Texas Instruments | LARGE T&R | 1 | $ 0.50 | |
| 100 | $ 0.34 | |||
| 250 | $ 0.26 | |||
| 1000 | $ 0.17 | |||
Description
General part information
SN74HCS273-Q1 Series
The SN74HCS273-Q1 device contains eight positive-edge-triggered D-type flip-flops with Schmitt-trigger inputs, shared asynchronous active low clear (CLR) input, and shared rising-edge triggered clock (CLK) input.
The SN74HCS273-Q1 device contains eight positive-edge-triggered D-type flip-flops with Schmitt-trigger inputs, shared asynchronous active low clear (CLR) input, and shared rising-edge triggered clock (CLK) input.
Documents
Technical documentation and resources
