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SSOP (DL)
Integrated Circuits (ICs)

SN74ABTH162260DL

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Texas Instruments

12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES WITH SERIES-DAMPING RESISTORS AND 3-STATE OUTPUTS

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SSOP (DL)
Integrated Circuits (ICs)

SN74ABTH162260DL

Active
Texas Instruments

12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCHES WITH SERIES-DAMPING RESISTORS AND 3-STATE OUTPUTS

Technical Specifications

Parameters and characteristics for this part

SpecificationSN74ABTH162260DL
Circuit12:24
Current - Output High, Low [custom]64 mA
Current - Output High, Low [custom]32 mA
Delay Time - Propagation3.6 ns
Independent Circuits1
Logic TypeD-Type Transparent Latch
Mounting TypeSurface Mount
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Output TypeTri-State
Package / Case0.295 in
Package / Case56-BSSOP
Package / Case7.5 mm
Supplier Device Package56-SSOP
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTube 320$ 3.05
Texas InstrumentsTUBE 1$ 3.30
100$ 2.89
250$ 2.03
1000$ 1.63

Description

General part information

SN74ABTH162260 Series

The 'ABTH162260 are 12-bit to 24-bit multiplexed D-type latches used in applications where two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demultiplexing of address and data information in microprocessor or bus-interface applications. These devices are also useful in memory-interleaving applications.

Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available for address and/or data transfer. The output-enable (OE1B\, OE2B\, and OEA\) inputs control the bus-transceiver functions. The OE1B\ and OE2B\ control signals also allow bank control in the A-to-B direction.

Address and/or data information can be stored using the internal storage latches. The latch-enable (LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage. When the latch-enable input is high, the latch is transparent. When the latch-enable input goes low, the data present at the inputs is latched and remains latched until the latch-enable input is returned high.

Documents

Technical documentation and resources

Implications of Slow or Floating CMOS Inputs (Rev. E)

Application note

Input and Output Characteristics of Digital Integrated Circuits

Application note

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Application note

Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A)

Application note

Quad Flatpack No-Lead Logic Packages (Rev. D)

Application note

Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B)

Application note

Selecting the Right Level Translation Solution (Rev. A)

Application note

Advanced Bus Interface Logic Selection Guide

Selection guide

Logic Guide (Rev. AB)

Selection guide

LOGIC Pocket Data Book (Rev. B)

User guide

12-Bit To 24-Bit Multiplexed D-Type Latches With Series-Damping Resistors datasheet (Rev. D)

Data sheet

Designing With Logic (Rev. C)

Application note

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Application note

Understanding Advanced Bus-Interface Products Design Guide

Application note

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Application note

TI IBIS File Creation, Validation, and Distribution Processes

Application note

Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A)

Application note

An Overview of Bus-Hold Circuit and the Applications (Rev. B)

Application note

Power-Up Behavior of Clocked Devices (Rev. B)

Application note

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

Application note

Live Insertion

Application note