Deep-Dive with AI
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Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | M38510/00203BCA |
|---|---|
| Clock Frequency | 20 MHz |
| Current - Output High, Low [custom] | 16 mA |
| Current - Output High, Low [custom] | 400 µA |
| Function | Reset |
| Max Propagation Delay @ V, Max CL | 40 ns |
| Mounting Type | Through Hole |
| Number of Bits per Element | 1 |
| Number of Elements | 2 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Output Type | Complementary |
| Package / Case | 14-CDIP |
| Supplier Device Package | 14-CDIP |
| Trigger Type | Positive Edge |
| Type | JK Type |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Texas Instruments | TUBE | 1 | $ 22.71 | |
| 100 | $ 19.84 | |||
| 250 | $ 15.30 | |||
| 1000 | $ 13.68 | |||
Description
General part information
SN54107 Series
The '107 contain two independent J-K flip-flops with individual J-K, clock, and direct clear inputs. The '107 is a positive pulse-triggered flip-flop. The J-K input data is loaded into the master while the clock is high and transferred to the slave and the outputs on the high-to-low clock transition. For these devices the J and K inputs must be stable while the clock is high.
The 'LS107A contain two independent negative-edge-triggered flip-flops. The J and K inputs must be stable prior to the high-to-low clock transition for predictable operation. When the clear is low, it overrides the clock and data inputs forcing the Q output low and the Q\ output high.
The SN54107 and the SN54LS107A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74107 and the SN74LS107A are characterized for operation from 0°C to 70°C.
Documents
Technical documentation and resources