
LPC3240FET296/01,5
UnknownARM MCU, LPC FAMILY LPC3000 SERIES MICROCONTROLLERS, ARM9, 32 BIT, 266 MHZ, 296 PINS
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LPC3240FET296/01,5
UnknownARM MCU, LPC FAMILY LPC3000 SERIES MICROCONTROLLERS, ARM9, 32 BIT, 266 MHZ, 296 PINS
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Technical Specifications
Parameters and characteristics for this part
| Specification | LPC3240FET296/01,5 |
|---|---|
| Connectivity | IrDA, Ethernet, SSI, EBI/EMI, Microwire, I2C, USB OTG, UART/USART, SPI, SSP |
| Core Processor | ARM926EJ-S |
| Core Size [Max] | 32 Bit |
| Core Size [Min] | 16 Bit |
| Data Converters [custom] | 3 |
| Data Converters [custom] | 10 b |
| Mounting Type | Surface Mount |
| Number of I/O | 51 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Oscillator Type | Internal |
| Package / Case | 296-TFBGA |
| Peripherals | WDT, DMA, PWM, Motor Control PWM, I2S |
| Program Memory Type | ROMless |
| RAM Size | 256 K |
| Speed | 266 MHz |
| Supplier Device Package | 296-TFBGA (15x15) |
| Voltage - Supply (Vcc/Vdd) [Max] | 3.6 V |
| Voltage - Supply (Vcc/Vdd) [Min] | 0.9 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Newark | Each | 1 | $ 11.33 | |
Description
General part information
LPC3240 Series
The LPC3240FET296/01,5 is a 16/32-bit Microcontroller based on ARM926EJ-S CPU core with a vector floating point co-processor and a large set of standard peripherals including USB On-The-Go. The device operates at CPU frequencies of up to 266MHz. The implementation uses an ARM926EJ-S CPU core with a Harvard architecture, 5-stage pipeline and an integral memory management unit (MMU). The MMU provides the virtual memory capabilities needed to support the multi-programming demands of modern operating systems. The ARM926EJ-S also has a hardware based set of DSP instruction extensions, which includes single cycle MAC operations and hardware based native Jazelle Java byte-code execution. The implementation has a 32kB instruction cache and a 32kB data cache. For low power consumption the device takes advantage of advanced technology development to optimize intrinsic power and uses software controlled architectural enhancements to optimize application based power management.
Documents
Technical documentation and resources