SN74ALVCH16823DLR
Active18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
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SN74ALVCH16823DLR
Active18-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74ALVCH16823DLR |
|---|---|
| Clock Frequency | 150 MHz |
| Current - Output High, Low | 24 mA |
| Input Capacitance | 4.5 pF |
| Max Propagation Delay @ V, Max CL | 4.5 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 9 |
| Number of Elements | 2 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Tri-State, Non-Inverted |
| Package / Case | 0.295 in |
| Package / Case | 56-BSSOP |
| Package / Case | 7.5 mm |
| Supplier Device Package | 56-SSOP |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 3.6 V |
| Voltage - Supply [Min] | 1.65 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 3.36 | |
| Digi-Reel® | 1 | $ 3.36 | ||
| Tape & Reel (TR) | 1000 | $ 1.77 | ||
| 2000 | $ 1.69 | |||
| 5000 | $ 1.62 | |||
| Texas Instruments | LARGE T&R | 1 | $ 2.54 | |
| 100 | $ 2.22 | |||
| 250 | $ 1.56 | |||
| 1000 | $ 1.25 | |||
Description
General part information
SN74ALVCH16823 Series
This 18-bit bus-interface flip-flop is designed for 1.65-V to 3.6-V VCCoperation.
The SN74ALVCH16823 features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. This device is particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.
The SN74ALVCH16823 can be used as two 9-bit flip-flops or one 18-bit flip-flop. With the clock-enable (CLKEN) input low, the D-type flip-flops enter data on the low-to-high transitions of the clock. TakingCLKENhigh disables the clock buffer, thus latching the outputs. Taking the clear (CLR) input low causes the Q outputs to go low independently of the clock.
Documents
Technical documentation and resources
