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JM38510/30901B2A
Integrated Circuits (ICs)

JM38510/36001B2A

Active
Texas Instruments

10-LINE TO 4-LINE AND 8-LINE TO 3-LINE PRIORITY ENCODERS

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JM38510/30901B2A
Integrated Circuits (ICs)

JM38510/36001B2A

Active
Texas Instruments

10-LINE TO 4-LINE AND 8-LINE TO 3-LINE PRIORITY ENCODERS

Technical Specifications

Parameters and characteristics for this part

SpecificationJM38510/36001B2A
Circuit [custom]3
Circuit [custom]8
Circuit [custom]1
Current - Output High, Low [custom]4 mA
Current - Output High, Low [custom]400 µA
Independent Circuits1
Mounting TypeSurface Mount
Operating Temperature [Max]125 °C
Operating Temperature [Min]-55 °C
Package / Case20-CLCC
Supplier Device Package20-LCCC (8.89x8.89)
TypePriority Encoder
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V
Voltage Supply SourceSingle Supply

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
Texas InstrumentsTUBE 1$ 41.74
100$ 36.46
250$ 28.11
1000$ 25.15

Description

General part information

SN54LS148 Series

These TTL encoders feature priority decoding of the inputs to ensure that only the highest-order data line is encoded. The '147 and 'LS147 encode nine data lines to four-line (8-4-2-1) BCD. The implied decimal zero condition requires no input condition as zero is encoded when all nine data lines are at a high logic level. The '148 and 'LS148 encode eight data lines to three-line (4-2-1) binary (octal). Cascading circuitry (enable input E1 and enable output E0) has been provided to allow octal expansion without the need for external circuitry. For all types, data inputs and outputs are active at the low logic level. All inputs are buffered to represent one normalized Series 54/74 or 54LS/74LS load, respectively.

These TTL encoders feature priority decoding of the inputs to ensure that only the highest-order data line is encoded. The '147 and 'LS147 encode nine data lines to four-line (8-4-2-1) BCD. The implied decimal zero condition requires no input condition as zero is encoded when all nine data lines are at a high logic level. The '148 and 'LS148 encode eight data lines to three-line (4-2-1) binary (octal). Cascading circuitry (enable input E1 and enable output E0) has been provided to allow octal expansion without the need for external circuitry. For all types, data inputs and outputs are active at the low logic level. All inputs are buffered to represent one normalized Series 54/74 or 54LS/74LS load, respectively.