
AFE5851IRGCR
Active16-CHANNEL VGA WITH ANALOG-TO-DIGITAL CONVERTER (ADC)
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AFE5851IRGCR
Active16-CHANNEL VGA WITH ANALOG-TO-DIGITAL CONVERTER (ADC)
Technical Specifications
Parameters and characteristics for this part
| Specification | AFE5851IRGCR |
|---|---|
| Mounting Type | Surface Mount |
| Number of Bits | 12 bits |
| Number of Channels | 16 |
| Package / Case | 64-VFQFN Exposed Pad |
| Power (Watts) | 633 mW |
| Supplier Device Package | 64-VQFN (9x9) |
| Voltage - Supply, Analog [Max] | 3.6 V, 1.9 V |
| Voltage - Supply, Analog [Min] | 1.7 V, 3 V |
| Voltage - Supply, Digital [Max] | 1.9 V |
| Voltage - Supply, Digital [Min] | 1.7 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tape & Reel (TR) | 2000 | $ 87.12 | |
| Texas Instruments | LARGE T&R | 1 | $ 92.70 | |
| 100 | $ 89.91 | |||
| 250 | $ 74.85 | |||
| 1000 | $ 69.70 | |||
Description
General part information
AFE5851 Series
The AFE5851 is an analog front-end targeting applications where the power and level of integration are critical. The device contains 16 variable gain amplifiers (VGA), followed by an octal high speed (up to 65 MSPS) analog to digital converter (ADC).
Each of the 16 single ended inputs is buffered, accepts up to 1VPPmaximum input swing and it is followed by a VGA with a gain range from –5dB to 31dB. The VGA gain is digitally controlled and the gain curves versus time can be stored in memory, integrated within the device using the serial interface.
A selectable clamping and anti-alias low pass filter (with 3dB attenuation at 7.5, 10 or 14MHz) is also integrated between the VGA and ADC for every channel. The VGA/anti-alias filter outputs are differential (limited to 2 VPP) and drive the on-board 12-bit 65MSPS ADC that is shared between two VGAs to optimize the power dissipation. Each VGA output is sampled at alternate clock cycles, making the effective sampling frequency half the input clock rate. The ADC also scales down its power consumption should a lower sampling rate be selected.
Documents
Technical documentation and resources