
TLC551CP
ActiveSTANDARD TIMER SINGLE 0°C 70°C 8-PIN PDIP TUBE
Deep-Dive with AI
Search across all available documentation for this part.

TLC551CP
ActiveSTANDARD TIMER SINGLE 0°C 70°C 8-PIN PDIP TUBE
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | TLC551CP |
|---|---|
| Current - Supply | 360 µA |
| Frequency | 1.8 MHz |
| Mounting Type | Through Hole |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Package / Case | 0.3 in |
| Package / Case | 8-DIP |
| Package / Case | 7.62 mm |
| Supplier Device Package | 8-PDIP |
| Type | 555 Type, Timer/Oscillator (Single) |
| Voltage - Supply [Max] | 15 V |
| Voltage - Supply [Min] | 1 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Arrow | N/A | 50 | $ 2.10 | |
| 100 | $ 1.94 | |||
| Digikey | Tube | 1 | $ 3.95 | |
| 10 | $ 2.60 | |||
| 25 | $ 2.25 | |||
| 100 | $ 1.86 | |||
| 250 | $ 1.66 | |||
| 500 | $ 1.55 | |||
| Texas Instruments | TUBE | 1 | $ 2.49 | |
| 100 | $ 2.06 | |||
| 250 | $ 1.48 | |||
| 1000 | $ 1.11 | |||
Description
General part information
TLC551 Series
The TLC551 is a monolithic timing circuit fabricated using the TI LinCMOSTM
timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Compared to the NE555 timer, this device uses smaller timing capacitors because of its high input impedance. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power supply voltage.
Like the NE555, the TLC551 has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between DISCH and GND. All unused inputs should be tied to an appropriate logic level to prevent false triggering.
Documents
Technical documentation and resources