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8-DIP
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TLC551CP

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Texas Instruments

STANDARD TIMER SINGLE 0°C 70°C 8-PIN PDIP TUBE

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8-DIP
Integrated Circuits (ICs)

TLC551CP

Active
Texas Instruments

STANDARD TIMER SINGLE 0°C 70°C 8-PIN PDIP TUBE

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationTLC551CP
Current - Supply360 µA
Frequency1.8 MHz
Mounting TypeThrough Hole
Operating Temperature [Max]70 °C
Operating Temperature [Min]0 °C
Package / Case0.3 in
Package / Case8-DIP
Package / Case7.62 mm
Supplier Device Package8-PDIP
Type555 Type, Timer/Oscillator (Single)
Voltage - Supply [Max]15 V
Voltage - Supply [Min]1 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
ArrowN/A 50$ 2.10
100$ 1.94
DigikeyTube 1$ 3.95
10$ 2.60
25$ 2.25
100$ 1.86
250$ 1.66
500$ 1.55
Texas InstrumentsTUBE 1$ 2.49
100$ 2.06
250$ 1.48
1000$ 1.11

Description

General part information

TLC551 Series

The TLC551 is a monolithic timing circuit fabricated using the TI LinCMOSTM

timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Compared to the NE555 timer, this device uses smaller timing capacitors because of its high input impedance. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power supply voltage.

Like the NE555, the TLC551 has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between DISCH and GND. All unused inputs should be tied to an appropriate logic level to prevent false triggering.

Documents

Technical documentation and resources