MC74HC4040ADR2G
ActiveCOUNTER, BINARY RIPPLE, 74HC, 50 MHZ, MAX COUNT 4095, 2 V TO 6 V, 16 PINS, SOIC
MC74HC4040ADR2G
ActiveCOUNTER, BINARY RIPPLE, 74HC, 50 MHZ, MAX COUNT 4095, 2 V TO 6 V, 16 PINS, SOIC
Technical Specifications
Parameters and characteristics for this part
| Specification | MC74HC4040ADR2G |
|---|---|
| Count Rate | 50 MHz |
| Direction | Up |
| Logic Type | Binary Counter |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 12 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 °C |
| Package / Case | 16-SOIC |
| Package / Case [x] | 0.154 in |
| Package / Case [y] | 3.9 mm |
| Reset | Asynchronous |
| Supplier Device Package | 16-SOIC |
| Trigger Type | Negative Edge |
| Voltage - Supply [Max] | 6 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 1.13 | |
| 10 | $ 0.67 | |||
| 25 | $ 0.56 | |||
| 100 | $ 0.43 | |||
| 250 | $ 0.37 | |||
| 500 | $ 0.34 | |||
| 1000 | $ 0.31 | |||
| Digi-Reel® | 1 | $ 1.13 | ||
| 10 | $ 0.67 | |||
| 25 | $ 0.56 | |||
| 100 | $ 0.43 | |||
| 250 | $ 0.37 | |||
| 500 | $ 0.34 | |||
| 1000 | $ 0.31 | |||
| Tape & Reel (TR) | 2500 | $ 0.28 | ||
| 5000 | $ 0.26 | |||
| 7500 | $ 0.25 | |||
| 12500 | $ 0.24 | |||
| 17500 | $ 0.23 | |||
| 25000 | $ 0.23 | |||
| Newark | Each (Supplied on Full Reel) | 1 | $ 0.31 | |
| 3000 | $ 0.30 | |||
| 6000 | $ 0.28 | |||
| 12000 | $ 0.26 | |||
| 18000 | $ 0.24 | |||
| 30000 | $ 0.23 | |||
| ON Semiconductor | N/A | 1 | $ 0.24 | |
Description
General part information
MC74HC4040A Series
The MC74C4040A is identical in pinout to the standard CMOS MC14040. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.This device consists of 12 master-slave flip-flops. The output of each flip-flop feeds the next and the frequency at each output is half of that of the preceding one. The state counter advances on the negative-going edge of the Clock input. Reset is asynchronous and active-high.State changes of the Q outputs do not occur simultaneously because of internal ripple delays. Therefore, decoded output signals are subject to decoding spikes and may have to be gated with the Clock of the HC4040A for some designs.
Documents
Technical documentation and resources
