
83056AGI-01LF
Obsolete6-BIT,2:1 SINGLE-ENDED LVCMOS MULTIPLEXER
Deep-Dive with AI
Search across all available documentation for this part.

83056AGI-01LF
Obsolete6-BIT,2:1 SINGLE-ENDED LVCMOS MULTIPLEXER
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | 83056AGI-01LF |
|---|---|
| Differential - Input:Output | False |
| Frequency - Max [Max] | 250 MHz |
| Input | LVCMOS, LVTTL |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output | LVCMOS, LVTTL |
| Package / Case | 20-TSSOP |
| Package / Case [x] | 0.173 in |
| Package / Case [y] | 4.4 mm |
| Ratio - Input:Output [custom] | 6 |
| Ratio - Input:Output [custom] | 2 |
| Supplier Device Package | 20-TSSOP |
| Type | Multiplexer |
| Voltage - Supply [Max] | 3.465 V |
| Voltage - Supply [Min] | 2.375 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 1 | $ 15.72 | |
| 10 | $ 12.45 | |||
| 74 | $ 10.90 | |||
Description
General part information
83056I-01 Series
The 83056I-01 is a 6-bit, 2:1, Single-ended LVCMOS Multiplexer and a member of the family of High Performance Clock Solutions from IDT. The 83056I-01 has two selectable single-ended LVCMOS clock inputs and six single-ended LVCMOS clock outputs. The outputs have a VDDO which may be set at 3.3V, 2.5V, or 1.8V, making the device ideal for use in voltage translation applications. An output enable pin places the output in a high impedance state which may be useful for testing or debug. Possible applications include systems with up to 6 transceivers which need to be independently set for different rates. For example, a board may have six transceivers, each of which need to be independently configured for 1 Gigabit Ethernet or 1 Gigabit Fibre Channel rates. Another possible application may require the ports to be independently set for FEC (Forward Error Correction) or non-FEC rates. The device operates up to 250MHz and is packaged in a 20 TSSOP.
Documents
Technical documentation and resources