Specification	SN5472J

Clock Frequency	20 MHz
Function	Reset, Set(Preset)
Max Propagation Delay @ V, Max CL	40 ns
Mounting Type	Through Hole
Number of Bits per Element	1
Number of Elements	1
Operating Temperature [Max]	125 °C
Operating Temperature [Min]	-55 °C
Output Type	Complementary
Package / Case	14-CDIP
Supplier Device Package	14-CDIP
Trigger Type	Positive Edge
Type	JK Type
Voltage - Supply [Max]	5.5 V
Voltage - Supply [Min]	4.5 V

SN5472 Series

And-Gated J-K Master-Slave Flip-Flops With Preset And Clear

Part	Trigger Type	Number of Elements	Clock Frequency	Type	Max Propagation Delay @ V, Max CL	Supplier Device Package	Number of Bits per Element	Voltage - Supply [Min]	Voltage - Supply [Max]	Function	Output Type	Mounting Type	Operating Temperature [Max]	Operating Temperature [Min]	Package / Case
Texas Instruments SN5472J	Positive Edge	1	20 MHz	JK Type	40 ns	14-CDIP	1	4.5 V	5.5 V	Reset Set(Preset)	Complementary	Through Hole	125 °C	-55 °C	14-CDIP

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Texas Instruments	TUBE	1	$ 14.05
		100	$ 12.27
		250	$ 9.46
		1000	$ 8.46

Description

General part information

SN5472 Series

These J-K flip-flops are based on the master-slave principle and each has AND gate inputs for entry into the master section which are controlled by the clock pulse. The clock pulse also regulates the state of the coupling transistors which connect the master and slave sections. The sequence of operation is as follows:

The logical states of the J and K inputs must not be allowed to change when the clock pulse is in a high state.

The SN5472, and the SN54H72 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN7472 is characterized for operation from 0°C to 70°C.

Documents

Technical documentation and resources

AND-Gated J-K Master-Slave Flip-Flops With Preset And Clear datasheet

Data sheet