ADS54J40IRMP
ActiveDUAL-CHANNEL, 14-BIT, 1.0-GSPS ANALOG-TO-DIGITAL CONVERTER (ADC)
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ADS54J40IRMP
ActiveDUAL-CHANNEL, 14-BIT, 1.0-GSPS ANALOG-TO-DIGITAL CONVERTER (ADC)
Technical Specifications
Parameters and characteristics for this part
| Specification | ADS54J40IRMP |
|---|---|
| Architecture | Pipelined |
| Configuration | S/H-ADC |
| Data Interface | JESD204B |
| Features | Simultaneous Sampling |
| Input Type | Differential |
| Mounting Type | Surface Mount |
| Number of A/D Converters | 2 |
| Number of Bits | 14 |
| Number of Inputs | 2 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 72-VFQFN Exposed Pad |
| Ratio - S/H:ADC | 1:1 |
| Reference Type | External |
| Sampling Rate (Per Second) | 1 G |
| Supplier Device Package | 72-VQFN (10x10) |
| Voltage - Supply, Analog [Max] | 2 V, 3.6 V |
| Voltage - Supply, Analog [Min] | 2.85 V, 1.8 V |
| Voltage - Supply, Digital [Max] | 2 V |
| Voltage - Supply, Digital [Min] | 1.7 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 1 | $ 700.96 | |
| 10 | $ 690.09 | |||
| Texas Instruments | JEDEC TRAY (5+1) | 1 | $ 624.08 | |
| 100 | $ 564.90 | |||
| 250 | $ 548.76 | |||
| 1000 | $ 538.00 | |||
Description
General part information
ADS54J40 Series
The ADS54J40 is a low-power, wide-bandwidth, 14-bit, 1.0-GSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –158 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10.0 Gbps, supporting two or four lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. Each ADC channel optionally can be connected to a wideband digital down-converter (DDC) block. The ADS54J40 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption.
The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 14-bit data from each channel.
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Documents
Technical documentation and resources