Deep-Dive with AI
Search across all available documentation for this part.
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | RM46L840ZWTT |
|---|---|
| Connectivity | Ethernet, SPI, LINbus, UART/USART, I2C, CANbus, SCI, EBI/EMI, MibSPI |
| Core Processor | ARM® Cortex®-R4F |
| Core Size [Max] | 32 Bit |
| Core Size [Min] | 16 Bit |
| Data Converters [custom] | 12 |
| Data Converters [custom] | 24 |
| EEPROM Size | 64 K |
| Mounting Type | Surface Mount |
| Number of I/O | 101 |
| Operating Temperature [Max] | 105 °C |
| Operating Temperature [Min] | -40 °C |
| Oscillator Type | External |
| Package / Case | 337-LFBGA |
| Peripherals | WDT, DMA, PWM, POR |
| Program Memory Size | 1.25 MB |
| Program Memory Type | FLASH |
| RAM Size | 192 K |
| Speed | 200 MHz |
| Supplier Device Package | 337-NFBGA (16x16) |
| Voltage - Supply (Vcc/Vdd) [Max] | 1.32 V |
| Voltage - Supply (Vcc/Vdd) [Min] | 1.14 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
Description
General part information
RM46L840 Series
The RM46Lx40 device is a high-performance microcontroller family for safety systems. The safety architecture includes dual CPUs in lockstep, CPU and memory BIST logic, ECC on both the flash and the data SRAM, parity on peripheral memories, and loopback capability on peripheral I/Os.
The RM46Lx40 device integrates the ARM Cortex-R4F floating-point CPU which offers an efficient 1.66 DMIPS/MHz, and can run up to 200 MHz providing up to 332 DMIPS. The device supports the little-endian [LE] format.
The RM46L840 device has 1.25MB of integrated flash and 192KB of data RAM with single-bit error correction and double-bit error detection. The RM46L440 device has 1MB of integrated flash and 128KB of data RAM with single-bit error correction and double-bit error detection. The flash memory on this device is a nonvolatile, electrically erasable and programmable memory, implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3-V supply input (same level as I/O supply) for all read, program, and erase operations. When in pipeline mode, the flash operates with a system clock frequency of up to 200 MHz. The SRAM supports single-cycle read and write accesses in byte, halfword, word, and double-word modes throughout the supported frequency range.
Documents
Technical documentation and resources
No documents available
