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40-WQFN-RTA
Integrated Circuits (ICs)

DRV8353FSRTAR

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Texas Instruments

102-V MAX 3-PHASE FUNCTIONAL SAFETY QUALITY-MANAGED SMART GATE DRIVER WITH 3X CSA

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40-WQFN-RTA
Integrated Circuits (ICs)

DRV8353FSRTAR

Active
Texas Instruments

102-V MAX 3-PHASE FUNCTIONAL SAFETY QUALITY-MANAGED SMART GATE DRIVER WITH 3X CSA

Technical Specifications

Parameters and characteristics for this part

SpecificationDRV8353FSRTAR
ApplicationsBrushless DC (BLDC)
Current - Output25 mA
FunctionController - Commutation, Direction Management
InterfaceSPI
Motor Type - AC, DCBrushless DC (BLDC)
Motor Type - StepperMultiphase
Mounting TypeSurface Mount
Operating Temperature [Max]125 °C
Operating Temperature [Min]-40 °C
Output ConfigurationPre-Driver - Half Bridge (3)
Package / Case40-WFQFN Exposed Pad
Supplier Device Package40-WQFN (6x6)
TechnologyPower MOSFET
Voltage - Load [Max]75 V
Voltage - Load [Min]9 V
Voltage - Supply [Max]100 V
Voltage - Supply [Min]7 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 6.20
10$ 5.57
25$ 5.26
100$ 4.56
250$ 4.33
500$ 3.88
1000$ 3.27
Digi-Reel® 1$ 6.20
10$ 5.57
25$ 5.26
100$ 4.56
250$ 4.33
500$ 3.88
1000$ 3.27
Tape & Reel (TR) 2000$ 3.11
Texas InstrumentsLARGE T&R 1$ 4.46
100$ 3.91
250$ 2.74
1000$ 2.21

Description

General part information

DRV8353R Series

The DRV8353M family of devices are highly-integrated gate drivers for three-phase brushless DC (BLDC) motor applications. These applications include field-oriented control (FOC), sinusoidal current control, and trapezoidal current control of BLDC motors. The device variants provide optional integrated current shunt amplifiers to support different motor control schemes and a buck regulator to power the gate driver or external controller.

The DRV8353M uses smart gate drive (SGD) architecture to decrease the number of external components that are typically necessary for MOSFET slew rate control and protection circuits. The SGD architecture also optimizes dead time to prevent shoot-through conditions, provides flexibility in decreasing electromagnetic interference (EMI) by MOSFET slew rate control, and protects against gate short circuit conditions through VGSmonitors. A strong gate pulldown circuit helps prevent unwanted dV/dt parasitic gate turn on events

Various PWM control modes (6x, 3x, 1x, and independent) are supported for simple interfacing to the external controller. These modes can decrease the number of outputs required of the controller for the motor driver PWM control signals. This family of devices also includes 1x PWM mode for simple sensored trapezoidal control of a BLDC motor by using an internal block commutation table.