Texas Instruments-SN74LVC2G00DCUT Logic Gates NAND Gate 2-Element 2-IN CMOS 8-Pin VSSOP T/R

Integrated Circuits (ICs)

SN74AVC2T45DCUTE4

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Texas Instruments

VOLTAGE LEVEL TRANSLATOR 2-CH BIDIRECTIONAL 8-PIN VSSOP T/R

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Integrated Circuits (ICs)

SN74AVC2T45DCUTE4

Unknown

Texas Instruments

VOLTAGE LEVEL TRANSLATOR 2-CH BIDIRECTIONAL 8-PIN VSSOP T/R

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Specifications Series Pricing Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	SN74AVC2T45DCUTE4

Channel Type	Bidirectional
Channels per Circuit	2
Data Rate	500 Mbps
Mounting Type	Surface Mount
Number of Circuits	1
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Output Type	Tri-State, Non-Inverted
Package / Case	8-VFSOP
Package / Case [y]	2.3 mm
Package / Case [y]	0.091 in
Translator Type	Voltage Level
Voltage - VCCA [Max]	3.6 V
Voltage - VCCA [Min]	1.2 V
Voltage - VCCB [Max]	3.6 V
Voltage - VCCB [Min]	1.2 V

SN74AVC2T45 Series

Dual-bit dual-supply bus transceiver with configurable voltage translation and 3-state outputs

Part	Voltage - VCCB [Max]	Voltage - VCCB [Min]	Data Rate	Translator Type	Number of Circuits	Output Type	Channel Type	Operating Temperature [Max]	Operating Temperature [Min]	Channels per Circuit	Supplier Device Package	Mounting Type	Voltage - VCCA [Min]	Voltage - VCCA [Max]	Package / Case	Package / Case [y]	Package / Case [y]
Texas Instruments SN74AVC2T45YEPR	3.6 V	1.2 V	500 Mbps	Voltage Level	1	Non-Inverted Tri-State	Bidirectional	85 °C	-40 °C	2	8-DSBGA	Surface Mount	1.2 V	3.6 V	8-XFBGA DSBGA
Texas Instruments SN74AVC2T45YZPR	3.6 V	1.2 V	500 Mbps	Voltage Level	1	Non-Inverted Tri-State	Bidirectional	85 °C	-40 °C	2	8-DSBGA	Surface Mount	1.2 V	3.6 V	8-XFBGA DSBGA
Texas Instruments SN74AVC2T45DCUT	3.6 V	1.2 V	500 Mbps	Voltage Level	1	Non-Inverted Tri-State	Bidirectional	85 °C	-40 °C	2		Surface Mount	1.2 V	3.6 V	8-VFSOP	2.3 mm	0.091 in
Texas Instruments SN74AVC2T45DCTT	3.6 V	1.2 V	500 Mbps	Voltage Level	1	Non-Inverted Tri-State	Bidirectional	85 °C	-40 °C	2	SM8	Surface Mount	1.2 V	3.6 V
Texas Instruments SN74AVC2T45DCUTE4	3.6 V	1.2 V	500 Mbps	Voltage Level	1	Non-Inverted Tri-State	Bidirectional	85 °C	-40 °C	2		Surface Mount	1.2 V	3.6 V	8-VFSOP	2.3 mm	0.091 in
Texas Instruments SN74AVC2T45DCURG4	3.6 V	1.2 V	500 Mbps	Voltage Level	1	Non-Inverted Tri-State	Bidirectional	85 °C	-40 °C	2		Surface Mount	1.2 V	3.6 V	8-VFSOP	2.3 mm	0.091 in
Texas Instruments SN74AVC2T45DCUTG4	3.6 V	1.2 V	500 Mbps	Voltage Level	1	Non-Inverted Tri-State	Bidirectional	85 °C	-40 °C	2		Surface Mount	1.2 V	3.6 V	8-VFSOP	2.3 mm	0.091 in
Texas Instruments SN74AVC2T45DCURE4	3.6 V	1.2 V	500 Mbps	Voltage Level	1	Non-Inverted Tri-State	Bidirectional	85 °C	-40 °C	2		Surface Mount	1.2 V	3.6 V	8-VFSOP	2.3 mm	0.091 in
Texas Instruments SN74AVC2T45DCTR	3.6 V	1.2 V	500 Mbps	Voltage Level	1	Non-Inverted Tri-State	Bidirectional	85 °C	-40 °C	2	SM8	Surface Mount	1.2 V	3.6 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tape & Reel (TR)	250	$ 0.74
		500	$ 0.65
		1250	$ 0.52
		2500	$ 0.48
		6250	$ 0.46
		12500	$ 0.44

Description

General part information

SN74AVC2T45 Series

This 2-bit non-inverting bus transceiver uses two separate configurable power-supply rails. The A ports are designed to track VCCA and accepts any supply voltage from 1.2V to 3.6V. The B ports are designed to track VCCB and accepts any supply voltage from 1.2V to 3.6V. This allows for universal low-voltage bidirectional translation and level-shifting between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes.

The SN74AVC2T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR pin) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess leakage current on the internal CMOS structure.

Documents

Technical documentation and resources

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