
MC74AC377DTR2G
ActiveIC,FLIP-FLOP,OCTAL,D TYPE,AC-CMOS,TSSOP,20PIN,PLASTIC
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MC74AC377DTR2G
ActiveIC,FLIP-FLOP,OCTAL,D TYPE,AC-CMOS,TSSOP,20PIN,PLASTIC
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Technical Specifications
Parameters and characteristics for this part
| Specification | MC74AC377DTR2G |
|---|---|
| Clock Frequency | 140 MHz |
| Current - Output High, Low | 24 mA |
| Current - Quiescent (Iq) | 8 ÁA |
| Function | Standard |
| Input Capacitance | 4.5 pF |
| Max Propagation Delay @ V, Max CL | 10 ns |
| Mounting Type | Surface Mount |
| Number of Bits per Element | 8 |
| Number of Elements | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output Type | Non-Inverted |
| Package / Case | 20-TSSOP |
| Package / Case [x] | 0.173 in |
| Package / Case [y] | 4.4 mm |
| Supplier Device Package | 20-TSSOP |
| Trigger Type | Positive Edge |
| Type | D-Type |
| Voltage - Supply [Max] | 6 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 1.56 | |
| 10 | $ 0.95 | |||
| 25 | $ 0.80 | |||
| 100 | $ 0.63 | |||
| 250 | $ 0.55 | |||
| 500 | $ 0.50 | |||
| 1000 | $ 0.46 | |||
| Digi-Reel® | 1 | $ 1.56 | ||
| 10 | $ 0.95 | |||
| 25 | $ 0.80 | |||
| 100 | $ 0.63 | |||
| 250 | $ 0.55 | |||
| 500 | $ 0.50 | |||
| 1000 | $ 0.46 | |||
| Tape & Reel (TR) | 2500 | $ 0.42 | ||
| 5000 | $ 0.39 | |||
| 7500 | $ 0.38 | |||
| 12500 | $ 0.37 | |||
| 17500 | $ 0.36 | |||
| Newark | Each (Supplied on Full Reel) | 1 | $ 0.35 | |
| 3000 | $ 0.34 | |||
| 6000 | $ 0.31 | |||
| 12000 | $ 0.29 | |||
| 18000 | $ 0.27 | |||
| 30000 | $ 0.26 | |||
| ON Semiconductor | N/A | 1 | $ 0.27 | |
Description
General part information
MC74AC377 Series
The MC74AC377/74ACT377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW.The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flipflop's Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation.
Documents
Technical documentation and resources