DDC3256ZWX
Active256 CHANNEL, 20-KSPS CURRENT-INPUT ANALOG-TO-DIGITAL CONVERTER
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DDC3256ZWX
Active256 CHANNEL, 20-KSPS CURRENT-INPUT ANALOG-TO-DIGITAL CONVERTER
Technical Specifications
Parameters and characteristics for this part
| Specification | DDC3256ZWX |
|---|---|
| Configuration | MUX-ADC |
| Data Interface | LVDS - Serial, SPI |
| Input Type | Single Ended |
| Mounting Type | Surface Mount |
| Number of A/D Converters | 2 |
| Number of Bits | 24 |
| Number of Inputs | 256 |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Package / Case | 336-LFBGA |
| Ratio - S/H:ADC | 0:2 |
| Reference Type | External |
| Sampling Rate (Per Second) | 20 k |
| Supplier Device Package | 336-NFBGA |
| Supplier Device Package [x] | 17.2 |
| Supplier Device Package [y] | 13.2 |
| Voltage - Supply, Analog | 1.85 V |
| Voltage - Supply, Digital | 1.85 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 108 | $ 324.42 | |
| Texas Instruments | EIAJ TRAY (10+1) | 1 | $ 288.84 | |
| 100 | $ 261.45 | |||
| 250 | $ 253.98 | |||
| 1000 | $ 249.00 | |||
Description
General part information
DDC3256 Series
The DDC3256 is a 24-bit, 256-channel, current-input analog-to-digital (A/D) converter. It combines both, current-to-voltage conversion by current integration, and A/D conversion.
Up to 256 individual low-level current output devices, such as photodiodes, can be directly connected to its inputs and digitized in parallel (simultaneously).
For each of the 256 inputs, the device has one low noise and low power integrator designed to capture all the charge from the sensor. The integration time is adjustable from 50 µs to 1.6 ms, allowing currents in the order of fA to µA to be continuously measured with outstanding precision. The outputs of the integrators are digitized by on-chip low power ADCs and the converted digital codes are transmitted over a single LVDS pair designed to minimize noise coupling in environments with high channel count.
Documents
Technical documentation and resources